^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel MID GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008-2014,2016 Intel Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Moorestown platform Langwell chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Medfield platform Penwell chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Clovertrail platform Cloverview chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define INTEL_MID_IRQ_TYPE_EDGE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define INTEL_MID_IRQ_TYPE_LEVEL (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Langwell chip has 64 pins and thus there are 2 32bit registers to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * registers to control them, so we only define the order here instead of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * structure, to get a bit offset for a pin (use GPDR as an example):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * nreg = ngpio / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * reg = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * bit = offset % 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * so the bit of reg_addr is to control pin offset's GPDR feature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum GPIO_REG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GPLR = 0, /* pin level read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GPDR, /* pin direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GPSR, /* pin set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GPCR, /* pin clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GRER, /* rising edge detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GFER, /* falling edge detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GEDR, /* edge detect result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GAFR, /* alt function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* intel_mid gpio driver data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct intel_mid_gpio_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 ngpio; /* number of gpio pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 chip_irq_type; /* chip interrupt type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct intel_mid_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum GPIO_REG reg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct intel_mid_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned nreg = chip->ngpio / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u8 reg = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return priv->reg_base + reg_type * nreg * 4 + reg * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) enum GPIO_REG reg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct intel_mid_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned nreg = chip->ngpio / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 reg = offset / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return priv->reg_base + reg_type * nreg * 4 + reg * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 value = readl(gafr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int shift = (offset % 16) << 1, af = (value >> shift) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (af) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) value &= ~(3 << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel(value, gafr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *gplr = gpio_reg(chip, offset, GPLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return !!(readl(gplr) & BIT(offset % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *gpsr, *gpcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gpsr = gpio_reg(chip, offset, GPSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel(BIT(offset % 32), gpsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) gpcr = gpio_reg(chip, offset, GPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writel(BIT(offset % 32), gpcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct intel_mid_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pm_runtime_get(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) value = readl(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) value &= ~BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel(value, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pm_runtime_put(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int intel_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct intel_mid_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) intel_gpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) pm_runtime_get(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) value = readl(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) value |= BIT(offset % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel(value, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pm_runtime_put(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int intel_mid_irq_type(struct irq_data *d, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct intel_mid_gpio *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 gpio = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (gpio >= priv->chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pm_runtime_get(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) value = readl(grer) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) value = readl(grer) & (~BIT(gpio % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) writel(value, grer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) value = readl(gfer) | BIT(gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) value = readl(gfer) & (~BIT(gpio % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(value, gfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (priv->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pm_runtime_put(&priv->pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static void intel_mid_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static void intel_mid_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct irq_chip intel_mid_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "INTEL_MID-GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .irq_mask = intel_mid_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .irq_unmask = intel_mid_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .irq_set_type = intel_mid_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct intel_mid_gpio_ddata gpio_lincroft = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ngpio = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct intel_mid_gpio_ddata gpio_penwell_aon = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .ngpio = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct intel_mid_gpio_ddata gpio_penwell_core = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ngpio = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const struct intel_mid_gpio_ddata gpio_cloverview_aon = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ngpio = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE | INTEL_MID_IRQ_TYPE_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct intel_mid_gpio_ddata gpio_cloverview_core = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ngpio = 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .chip_irq_type = INTEL_MID_IRQ_TYPE_EDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct pci_device_id intel_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Lincroft */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .driver_data = (kernel_ulong_t)&gpio_lincroft,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Penwell AON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .driver_data = (kernel_ulong_t)&gpio_penwell_aon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Penwell Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .driver_data = (kernel_ulong_t)&gpio_penwell_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Cloverview Aon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08eb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .driver_data = (kernel_ulong_t)&gpio_cloverview_aon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Cloverview Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x08f7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .driver_data = (kernel_ulong_t)&gpio_cloverview_core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void intel_mid_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct intel_mid_gpio *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct irq_data *data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct irq_chip *chip = irq_data_get_irq_chip(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 base, gpio, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void __iomem *gedr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* check GPIO controller to check which pin triggered the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (base = 0; base < priv->chip.ngpio; base += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) gedr = gpio_reg(&priv->chip, base, GEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) while ((pending = readl(gedr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) gpio = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mask = BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Clear before handling so we can't lose an edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) writel(mask, gedr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) generic_handle_irq(irq_find_mapping(gc->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) base + gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) chip->irq_eoi(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int intel_mid_irq_init_hw(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct intel_mid_gpio *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (base = 0; base < priv->chip.ngpio; base += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Clear the rising-edge detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) reg = gpio_reg(&priv->chip, base, GRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Clear the falling-edge detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg = gpio_reg(&priv->chip, base, GFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Clear the edge detect status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) reg = gpio_reg(&priv->chip, base, GEDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel(~0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int __maybe_unused intel_gpio_runtime_idle(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int err = pm_schedule_suspend(dev, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err ?: -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct dev_pm_ops intel_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SET_RUNTIME_PM_OPS(NULL, NULL, intel_gpio_runtime_idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static int intel_gpio_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct intel_mid_gpio *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) u32 irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct intel_mid_gpio_ddata *ddata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) (struct intel_mid_gpio_ddata *)id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) retval = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) retval = pcim_iomap_regions(pdev, 1 << 0 | 1 << 1, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(&pdev->dev, "I/O memory mapping error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) base = pcim_iomap_table(pdev)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) irq_base = readl(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gpio_base = readl(sizeof(u32) + base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* release the IO mapping, since we already get the info from bar1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pcim_iounmap_regions(pdev, 1 << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) priv->reg_base = pcim_iomap_table(pdev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) priv->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) priv->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->chip.request = intel_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) priv->chip.direction_input = intel_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) priv->chip.direction_output = intel_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) priv->chip.get = intel_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) priv->chip.set = intel_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) priv->chip.base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) priv->chip.ngpio = ddata->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) priv->chip.can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) girq = &priv->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) girq->chip = &intel_mid_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) girq->init_hw = intel_mid_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) girq->parent_handler = intel_mid_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) girq->parents[0] = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) girq->first = irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pci_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_err(&pdev->dev, "gpiochip_add error %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pm_runtime_allow(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct pci_driver intel_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "intel_mid_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .id_table = intel_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .probe = intel_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pm = &intel_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) builtin_pci_driver(intel_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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