^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Extreme Engineering Solutions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/lpc_ich.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DRV_NAME "gpio_ich"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * GPIO register offsets in GPIO I/O space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * LVLx registers. Logic in the read/write functions takes a register and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * an absolute bit number and determines the proper register offset and bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * number in that register. For example, to read the value of GPIO bit 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * bit 18 (50%32).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum GPIO_REG {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GPIO_USE_SEL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) GPIO_IO_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GPIO_LVL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GPO_BLINK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const u8 ichx_regs[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {0x18, 0x18, 0x18}, /* BLINK offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const u8 ichx_reglen[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 0x30, 0x10, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static const u8 avoton_regs[4][3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {0x00, 0x80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {0x04, 0x84, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {0x08, 0x88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static const u8 avoton_reglen[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 0x10, 0x10, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct ichx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Max GPIO pins the chipset can have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) uint ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* chipset registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const u8 (*regs)[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) const u8 *reglen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* GPO_BLINK is available on this chipset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool have_blink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bool uses_gpe0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* USE_SEL is bogus on some chipsets, eg 3100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 use_sel_ignore[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Some chipsets have quirks, let these use their own request/get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int (*request)(struct gpio_chip *chip, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int (*get)(struct gpio_chip *chip, unsigned int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Some chipsets don't let reading output values on GPIO_LVL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * this option allows driver caching written output values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bool use_outlvl_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct resource *gpio_base; /* GPIO IO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct resource *pm_base; /* Power Management IO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct ichx_desc *desc; /* Pointer to chipset-specific description */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 use_gpio; /* Which GPIO groups are usable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int outlvl_cache[3]; /* cached output values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } ichx_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int modparam_gpiobase = -1; /* dynamic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) module_param_named(gpiobase, modparam_gpiobase, int, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int ichx_write_bit(int reg, unsigned int nr, int val, int verify)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 data, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int reg_nr = nr / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int bit = nr & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_lock_irqsave(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) data = ichx_priv.outlvl_cache[reg_nr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ichx_priv.gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) data |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) data &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ichx_priv.gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ichx_priv.outlvl_cache[reg_nr] = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) ichx_priv.gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) spin_unlock_irqrestore(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return (verify && data != tmp) ? -EPERM : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int ichx_read_bit(int reg, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int reg_nr = nr / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int bit = nr & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_lock_irqsave(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ichx_priv.gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) data = ichx_priv.outlvl_cache[reg_nr] | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_unlock_irqrestore(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return !!(data & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return !!(ichx_priv.use_gpio & BIT(nr / 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ichx_read_bit(GPIO_IO_SEL, nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Try setting pin as an input and verify it worked since many pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * are output-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Disable blink hardware which is available for GPIOs from 0 to 31. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (nr < 32 && ichx_priv.desc->have_blink)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ichx_write_bit(GPO_BLINK, nr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Set GPIO output value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ichx_write_bit(GPIO_LVL, nr, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Try setting pin as an output and verify it worked since many pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * are input-only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int ichx_gpio_get(struct gpio_chip *chip, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ichx_read_bit(GPIO_LVL, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int ich6_gpio_get(struct gpio_chip *chip, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * GPI 0 - 15 need to be read from the power management registers on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * a ICH6/3100 bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (nr < 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!ichx_priv.pm_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) spin_lock_irqsave(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* GPI 0 - 15 are latched, write 1 to clear*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) data = ICHX_READ(0, ichx_priv.pm_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_unlock_irqrestore(&ichx_priv.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return !!((data >> 16) & BIT(nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return ichx_gpio_get(chip, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ichx_gpio_request(struct gpio_chip *chip, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!ichx_gpio_check_available(chip, nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Note we assume the BIOS properly set a bridge's USE value. Some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * chips (eg Intel 3100) have bogus USE values though, so first see if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * the chipset's USE value can be trusted for this specific bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * If it can't be trusted, assume that the pin can be used as a GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int ich6_gpio_request(struct gpio_chip *chip, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * bridge as they are controlled by USE register bits 0 and 1. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * additional info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (nr == 16 || nr == 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) nr -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ichx_gpio_request(chip, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void ichx_gpio_set(struct gpio_chip *chip, unsigned int nr, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ichx_write_bit(GPIO_LVL, nr, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void ichx_gpiolib_setup(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) chip->label = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) chip->parent = ichx_priv.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Allow chip-specific overrides of request()/get() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) chip->request = ichx_priv.desc->request ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ichx_priv.desc->request : ichx_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) chip->get = ichx_priv.desc->get ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ichx_priv.desc->get : ichx_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) chip->set = ichx_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) chip->get_direction = ichx_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) chip->direction_input = ichx_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) chip->direction_output = ichx_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) chip->base = modparam_gpiobase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) chip->ngpio = ichx_priv.desc->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) chip->can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) chip->dbg_show = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* ICH6-based, 631xesb-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct ichx_desc ich6_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .request = ich6_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .get = ich6_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* GPIO 0-15 are read in the GPE0_STS PM register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .uses_gpe0 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .ngpio = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .have_blink = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Intel 3100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct ichx_desc i3100_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Datasheet for more info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .use_sel_ignore = {0x00130000, 0x00010000, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* The 3100 needs fixups for GPIO 0 - 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .request = ich6_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .get = ich6_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* GPIO 0-15 are read in the GPE0_STS PM register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .uses_gpe0 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ngpio = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* ICH7 and ICH8-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct ichx_desc ich7_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .ngpio = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .have_blink = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* ICH9-based */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct ichx_desc ich9_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .ngpio = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .have_blink = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* ICH10-based - Consumer/corporate versions have different amount of GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static struct ichx_desc ich10_cons_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .ngpio = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .have_blink = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct ichx_desc ich10_corp_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .ngpio = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .have_blink = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Intel 5 series, 6 series, 3400 series, and C200 series */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct ichx_desc intel5_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .ngpio = 76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .regs = ichx_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .reglen = ichx_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* Avoton */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct ichx_desc avoton_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* Avoton has only 59 GPIOs, but we assume the first set of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * (Core) has 32 instead of 31 to keep gpio-ich compliance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .ngpio = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .regs = avoton_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .reglen = avoton_reglen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .use_outlvl_cache = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int ichx_gpio_request_regions(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct resource *res_base, const char *name, u8 use_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!res_base || !res_base->start || !res_base->end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!(use_gpio & BIT(i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!devm_request_region(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) res_base->start + ichx_priv.desc->regs[0][i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ichx_priv.desc->reglen[i], name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int ichx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct lpc_ich_info *ich_info = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct resource *res_base, *res_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!ich_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) switch (ich_info->gpio_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case ICH_I3100_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ichx_priv.desc = &i3100_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case ICH_V5_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ichx_priv.desc = &intel5_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case ICH_V6_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ichx_priv.desc = &ich6_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) case ICH_V7_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ichx_priv.desc = &ich7_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case ICH_V9_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ichx_priv.desc = &ich9_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) case ICH_V10CORP_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ichx_priv.desc = &ich10_corp_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case ICH_V10CONS_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ichx_priv.desc = &ich10_cons_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case AVOTON_GPIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ichx_priv.desc = &avoton_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ichx_priv.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) spin_lock_init(&ichx_priv.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) err = ichx_gpio_request_regions(dev, res_base, pdev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ich_info->use_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ichx_priv.gpio_base = res_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ichx_priv.use_gpio = ich_info->use_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * If necessary, determine the I/O address of ACPI/power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * registers which are needed to read the GPE0 register for GPI pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * 0 - 15 on some chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!ichx_priv.desc->uses_gpe0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!res_pm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!devm_request_region(dev, res_pm->start, resource_size(res_pm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) goto init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ichx_priv.pm_base = res_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ichx_gpiolib_setup(&ichx_priv.chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = gpiochip_add_data(&ichx_priv.chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev_err(dev, "Failed to register GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ichx_priv.chip.base + ichx_priv.chip.ngpio - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int ichx_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) gpiochip_remove(&ichx_priv.chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct platform_driver ichx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .probe = ichx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .remove = ichx_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) module_platform_driver(ichx_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MODULE_ALIAS("platform:"DRV_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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