^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Support for the GPIO/IRQ expander chips present on several HTC phones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * These are implemented in CPLD chips present on the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2007 Kevin O'Connor <kevin@koconnor.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007 Philipp Zabel <philipp.zabel@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file may be distributed under the terms of the GNU GPL license.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/gpio-htc-egpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct egpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) int reg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int cached_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct egpio_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* iomem info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int bus_shift; /* byte shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int reg_shift; /* bit shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int reg_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* irq info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ack_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int ack_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u16 irqs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) uint irq_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) uint chained_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* egpio info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct egpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int nchips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static inline void egpio_writew(u16 value, struct egpio_info *ei, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writew(value, ei->base_addr + (reg << ei->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline u16 egpio_readw(struct egpio_info *ei, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return readw(ei->base_addr + (reg << ei->bus_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * IRQs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void ack_irqs(struct egpio_info *ei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) egpio_writew(ei->ack_write, ei, ei->ack_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pr_debug("EGPIO ack - write %x to base+%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ei->ack_write, ei->ack_register << ei->bus_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void egpio_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* There does not appear to be a way to proactively mask interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * on the egpio chip itself. So, we simply ignore interrupts that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * aren't desired. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void egpio_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct egpio_info *ei = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ei->irqs_enabled &= ~(1 << (data->irq - ei->irq_start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pr_debug("EGPIO mask %d %04x\n", data->irq, ei->irqs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void egpio_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct egpio_info *ei = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ei->irqs_enabled |= 1 << (data->irq - ei->irq_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pr_debug("EGPIO unmask %d %04x\n", data->irq, ei->irqs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct irq_chip egpio_muxed_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = "htc-egpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .irq_ack = egpio_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .irq_mask = egpio_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .irq_unmask = egpio_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void egpio_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct egpio_info *ei = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int irqpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Read current pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long readval = egpio_readw(ei, ei->ack_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_debug("IRQ reg: %x\n", (unsigned int)readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Ack/unmask interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ack_irqs(ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Process all set pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) readval &= ei->irqs_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) for_each_set_bit(irqpin, &readval, ei->nirqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Run irq handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) pr_debug("got IRQ %d\n", irqpin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) generic_handle_irq(ei->irq_start + irqpin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline int egpio_pos(struct egpio_info *ei, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return bit >> ei->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static inline int egpio_bit(struct egpio_info *ei, int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 1 << (bit & ((1 << ei->reg_shift)-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Input pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int egpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct egpio_info *ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pr_debug("egpio_get_value(%d)\n", chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ei = dev_get_drvdata(egpio->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bit = egpio_bit(ei, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = egpio->reg_start + egpio_pos(ei, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (test_bit(offset, &egpio->is_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return !!(egpio->cached_values & (1 << offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) value = egpio_readw(ei, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pr_debug("readw(%p + %x) = %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ei->base_addr, reg << ei->bus_shift, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return !!(value & bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int egpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return test_bit(offset, &egpio->is_out) ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Output pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void egpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct egpio_info *ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) pr_debug("egpio_set(%s, %d(%d), %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) chip->label, offset, offset+chip->base, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ei = dev_get_drvdata(egpio->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pos = egpio_pos(ei, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) reg = egpio->reg_start + pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) shift = pos << ei->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) pr_debug("egpio %s: reg %d = 0x%04x\n", value ? "set" : "clear",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) reg, (egpio->cached_values >> shift) & ei->reg_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) spin_lock_irqsave(&ei->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) egpio->cached_values |= (1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) egpio->cached_values &= ~(1 << offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) egpio_writew((egpio->cached_values >> shift) & ei->reg_mask, ei, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&ei->lock, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int egpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (test_bit(offset, &egpio->is_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) egpio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int egpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (test_bit(offset, &egpio->is_out))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void egpio_write_cache(struct egpio_info *ei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct egpio_chip *egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) for (i = 0; i < ei->nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) egpio = &(ei->chip[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!egpio->is_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) for (shift = 0; shift < egpio->chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) shift += (1<<ei->reg_shift)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int reg = egpio->reg_start + egpio_pos(ei, shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!((egpio->is_out >> shift) & ei->reg_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_debug("EGPIO: setting %x to %x, was %x\n", reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) (egpio->cached_values >> shift) & ei->reg_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) egpio_readw(ei, reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) egpio_writew((egpio->cached_values >> shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) & ei->reg_mask, ei, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int __init egpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct htc_egpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct egpio_info *ei;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int irq, irq_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Initialize ei data structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ei = devm_kzalloc(&pdev->dev, sizeof(*ei), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (!ei)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) spin_lock_init(&ei->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Find chained irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ei->chained_irq = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Map egpio chip into virtual address space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ei->base_addr = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (IS_ERR(ei->base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return PTR_ERR(ei->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if ((pdata->bus_width != 16) && (pdata->bus_width != 32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ei->bus_shift = fls(pdata->bus_width - 1) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pr_debug("bus_shift = %d\n", ei->bus_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if ((pdata->reg_width != 8) && (pdata->reg_width != 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ei->reg_shift = fls(pdata->reg_width - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pr_debug("reg_shift = %d\n", ei->reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ei->reg_mask = (1 << pdata->reg_width) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) platform_set_drvdata(pdev, ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ei->nchips = pdata->num_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ei->chip = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ei->nchips, sizeof(struct egpio_chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!ei->chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) for (i = 0; i < ei->nchips; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ei->chip[i].reg_start = pdata->chip[i].reg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ei->chip[i].cached_values = pdata->chip[i].initial_values;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ei->chip[i].is_out = pdata->chip[i].direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ei->chip[i].dev = &(pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) chip = &(ei->chip[i].chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) chip->label = devm_kasprintf(&pdev->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "htc-egpio-%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (!chip->label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) chip->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) chip->get = egpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) chip->set = egpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) chip->direction_input = egpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) chip->direction_output = egpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) chip->get_direction = egpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) chip->base = pdata->chip[i].gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) chip->ngpio = pdata->chip[i].num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) gpiochip_add_data(chip, &ei->chip[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Set initial pin values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) egpio_write_cache(ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ei->irq_start = pdata->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ei->nirqs = pdata->num_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ei->ack_register = pdata->ack_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (ei->chained_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Setup irq handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ei->ack_write = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (pdata->invert_acks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ei->ack_write = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_end = ei->irq_start + ei->nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) for (irq = ei->irq_start; irq < irq_end; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) irq_set_chip_and_handler(irq, &egpio_muxed_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) irq_set_chip_data(irq, ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) irq_set_irq_type(ei->chained_irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) irq_set_chained_handler_and_data(ei->chained_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) egpio_handler, ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ack_irqs(ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) device_init_wakeup(&pdev->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int egpio_suspend(struct platform_device *pdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct egpio_info *ei = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ei->chained_irq && device_may_wakeup(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) enable_irq_wake(ei->chained_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int egpio_resume(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct egpio_info *ei = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ei->chained_irq && device_may_wakeup(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) disable_irq_wake(ei->chained_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Update registers from the cache, in case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) the CPLD was powered off during suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) egpio_write_cache(ei);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define egpio_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define egpio_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct platform_driver egpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .name = "htc-egpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .suspend = egpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .resume = egpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int __init egpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return platform_driver_probe(&egpio_driver, egpio_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* start early for dependencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) subsys_initcall(egpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags