^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2008-2009 The GameCube Linux Team
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2008,2009 Albert Herranz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright (C) 2017-2018 Jonathan Neuschäfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Nintendo Wii (Hollywood) GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Register names and offsets courtesy of WiiBrew:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * https://wiibrew.org/wiki/Hardware/Hollywood_GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Note that for most registers, there are two versions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * - HW_GPIOB_* Is always accessible by the Broadway PowerPC core, but does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * always give access to all GPIO lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * - HW_GPIO_* Is only accessible by the Broadway PowerPC code if the memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * firewall (AHBPROT) in the Hollywood chipset has been configured to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * such access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The ownership of each GPIO line can be configured in the HW_GPIO_OWNER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * register: A one bit configures the line for access via the HW_GPIOB_*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * registers, a zero bit indicates access via HW_GPIO_*. This driver uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * HW_GPIOB_*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HW_GPIOB_OUT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HW_GPIOB_DIR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HW_GPIOB_IN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HW_GPIOB_INTLVL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HW_GPIOB_INTFLAG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HW_GPIOB_INTMASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HW_GPIOB_INMIR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HW_GPIO_ENABLE 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HW_GPIO_OUT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HW_GPIO_DIR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HW_GPIO_IN 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HW_GPIO_INTLVL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HW_GPIO_INTFLAG 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HW_GPIO_INTMASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HW_GPIO_INMIR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HW_GPIO_OWNER 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct hlwd_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct gpio_chip gpioc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct irq_chip irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 edge_emulation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 rising_edge, falling_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void hlwd_gpio_irqhandler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct hlwd_gpio *hlwd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) gpiochip_get_data(irq_desc_get_handler_data(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 emulated_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pending = ioread32be(hlwd->regs + HW_GPIOB_INTFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pending &= ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Treat interrupts due to edge trigger emulation separately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) emulated_pending = hlwd->edge_emulation & pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pending &= ~emulated_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (emulated_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 level, rising, falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) rising = level & emulated_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) falling = ~level & emulated_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Invert the levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) iowrite32be(level ^ emulated_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Ack all emulated-edge interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) iowrite32be(emulated_pending, hlwd->regs + HW_GPIOB_INTFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Signal interrupts only on the correct edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rising &= hlwd->rising_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) falling &= hlwd->falling_edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Mark emulated interrupts as pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pending |= rising | falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) for_each_set_bit(hwirq, &pending, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int irq = irq_find_mapping(hlwd->gpioc.irq.domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void hlwd_gpio_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct hlwd_gpio *hlwd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iowrite32be(BIT(data->hwirq), hlwd->regs + HW_GPIOB_INTFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void hlwd_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct hlwd_gpio *hlwd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mask &= ~BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void hlwd_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct hlwd_gpio *hlwd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mask = ioread32be(hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mask |= BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) iowrite32be(mask, hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static void hlwd_gpio_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hlwd_gpio_irq_ack(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hlwd_gpio_irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void hlwd_gpio_irq_setup_emulation(struct hlwd_gpio *hlwd, int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 level, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Set the trigger level to the inactive level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) state = ioread32be(hlwd->regs + HW_GPIOB_IN) & BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) level &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) level |= state ^ BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) hlwd->edge_emulation |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) hlwd->rising_edge &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) hlwd->falling_edge &= ~BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (flow_type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) hlwd->rising_edge |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (flow_type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hlwd->falling_edge |= BIT(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int hlwd_gpio_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct hlwd_gpio *hlwd =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) spin_lock_irqsave(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) hlwd->edge_emulation &= ~BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) level |= BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) level = ioread32be(hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) level &= ~BIT(data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) iowrite32be(level, hlwd->regs + HW_GPIOB_INTLVL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hlwd_gpio_irq_setup_emulation(hlwd, data->hwirq, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) spin_unlock_irqrestore(&hlwd->gpioc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int hlwd_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct hlwd_gpio *hlwd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) hlwd = devm_kzalloc(&pdev->dev, sizeof(*hlwd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (!hlwd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) hlwd->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (IS_ERR(hlwd->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return PTR_ERR(hlwd->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * Claim all GPIOs using the OWNER register. This will not work on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * systems where the AHBPROT memory firewall hasn't been configured to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * permit PPC access to HW_GPIO_*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Note that this has to happen before bgpio_init reads the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * HW_GPIOB_OUT and HW_GPIOB_DIR, because otherwise it reads the wrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) iowrite32be(0xffffffff, hlwd->regs + HW_GPIO_OWNER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) res = bgpio_init(&hlwd->gpioc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) hlwd->regs + HW_GPIOB_IN, hlwd->regs + HW_GPIOB_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) NULL, hlwd->regs + HW_GPIOB_DIR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) BGPIOF_BIG_ENDIAN_BYTE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (res < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_warn(&pdev->dev, "bgpio_init failed: %d\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) res = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ngpios = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) hlwd->gpioc.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Mask and ack all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) iowrite32be(0, hlwd->regs + HW_GPIOB_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) iowrite32be(0xffffffff, hlwd->regs + HW_GPIOB_INTFLAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * If this GPIO controller is not marked as an interrupt controller in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * the DT, skip interrupt support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) hlwd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (hlwd->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_info(&pdev->dev, "platform_get_irq returned %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) hlwd->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return hlwd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) hlwd->irqc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) hlwd->irqc.irq_mask = hlwd_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) hlwd->irqc.irq_unmask = hlwd_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) hlwd->irqc.irq_enable = hlwd_gpio_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hlwd->irqc.irq_set_type = hlwd_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) girq = &hlwd->gpioc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) girq->chip = &hlwd->irqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) girq->parent_handler = hlwd_gpio_irqhandler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) girq->parents[0] = hlwd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return devm_gpiochip_add_data(&pdev->dev, &hlwd->gpioc, hlwd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct of_device_id hlwd_gpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { .compatible = "nintendo,hollywood-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MODULE_DEVICE_TABLE(of, hlwd_gpio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct platform_driver hlwd_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "gpio-hlwd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .of_match_table = hlwd_gpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .probe = hlwd_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) module_platform_driver(hlwd_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_AUTHOR("Jonathan Neuschäfer <j.neuschaefer@gmx.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_DESCRIPTION("Nintendo Wii GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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