^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 2013 (c) Aeroflex Gaisler AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * IP core library.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Full documentation of the GRGPIO core can be found here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://www.gaisler.com/products/grlib/grip.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * information on open firmware properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Contributors: Andreas Larsson <andreas@gaisler.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GRGPIO_MAX_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GRGPIO_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GRGPIO_OUTPUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GRGPIO_DIR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GRGPIO_IMASK 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GRGPIO_IPOL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GRGPIO_IEDGE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GRGPIO_BYPASS 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GRGPIO_IMAP_BASE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Structure for an irq of the core - called an underlying irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct grgpio_uirq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 uirq; /* Underlying irq of the gpio driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Structure for an irq of a gpio line handed out by this driver. The index is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * used to map to the corresponding underlying irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct grgpio_lirq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u8 irq; /* irq for the gpio line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct grgpio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 imask; /* irq mask shadow register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * The grgpio core can have multiple "underlying" irqs. The gpio lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * can be mapped to any one or none of these underlying irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * independently of each other. This driver sets up an irq domain and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * hands out separate irqs to each gpio line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * This array contains information on each underlying irq, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * irq of the grgpio core itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * This array contains information for each gpio line on the irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * obtains from this driver. An index value of -1 for a certain gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * line indicates that the line has no irq. Otherwise the index connects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * the irq to the underlying irq by pointing into the uirqs array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct gpio_chip *gc = &priv->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) priv->imask |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) priv->imask &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct grgpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (offset >= gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (priv->lirqs[offset].index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return irq_create_mapping(priv->domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* -------------------- IRQ chip functions -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 ipol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 iedge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) edge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pol = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) edge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) edge = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pol = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) edge = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void grgpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) grgpio_set_imask(priv, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void grgpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) grgpio_set_imask(priv, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct irq_chip grgpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "grgpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .irq_mask = grgpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .irq_unmask = grgpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .irq_set_type = grgpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static irqreturn_t grgpio_irq_handler(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct grgpio_priv *priv = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ngpio = priv->gc.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int match = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * For each gpio line, call its interrupt handler if it its underlying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * irq matches the current irq that is handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct grgpio_lirq *lirq = &priv->lirqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (priv->imask & BIT(i) && lirq->index >= 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) priv->uirqs[lirq->index].uirq == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) generic_handle_irq(lirq->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) match = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * This function will be called as a consequence of the call to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * irq_create_mapping in grgpio_to_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct grgpio_priv *priv = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct grgpio_lirq *lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct grgpio_uirq *uirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int offset = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) lirq = &priv->lirqs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (lirq->index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) irq, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Request underlying irq if not already requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) lirq->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) uirq = &priv->uirqs[lirq->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (uirq->refcnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) dev_name(priv->dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "Could not request underlying irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) uirq->uirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) uirq->refcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Setup irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) irq_set_chip_data(irq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) irq_set_chip_and_handler(irq, &grgpio_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct grgpio_priv *priv = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct grgpio_lirq *lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct grgpio_uirq *uirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int ngpio = priv->gc.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) irq_set_chip_and_handler(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Free underlying irq if last user unmapped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) for (i = 0; i < ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) lirq = &priv->lirqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (lirq->irq == irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) grgpio_set_imask(priv, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) lirq->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) index = lirq->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) WARN_ON(index < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (index >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uirq = &priv->uirqs[lirq->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uirq->refcnt--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (uirq->refcnt == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) free_irq(uirq->uirq, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct irq_domain_ops grgpio_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .map = grgpio_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .unmap = grgpio_irq_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int grgpio_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct grgpio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) s32 *irqmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) regs = devm_platform_ioremap_resource(ofdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (IS_ERR(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return PTR_ERR(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gc = &priv->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BGPIOF_BIG_ENDIAN_BYTE_ORDER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_err(&ofdev->dev, "bgpio_init() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) priv->dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) gc->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) gc->to_irq = grgpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) gc->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) err = of_property_read_u32(np, "nbits", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) gc->ngpio = GRGPIO_MAX_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_dbg(&ofdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "No or invalid nbits property: assume %d\n", gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) gc->ngpio = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * The irqmap contains the index values indicating which underlying irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * if anyone, is connected to that line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) irqmap = (s32 *)of_get_property(np, "irqmap", &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (irqmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (size < gc->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(&ofdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "irqmap shorter than ngpio (%d < %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) size, gc->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) priv->domain = irq_domain_add_linear(np, gc->ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) &grgpio_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!priv->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(&ofdev->dev, "Could not add irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for (i = 0; i < gc->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct grgpio_lirq *lirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) lirq = &priv->lirqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) lirq->index = irqmap[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (lirq->index < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = platform_get_irq(ofdev, lirq->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Continue without irq functionality for that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * gpio line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) priv->uirqs[lirq->index].uirq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) platform_set_drvdata(ofdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err = gpiochip_add_data(gc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev_err(&ofdev->dev, "Could not add gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (priv->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int grgpio_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct grgpio_priv *priv = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (priv->domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (priv->uirqs[i].refcnt != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) gpiochip_remove(&priv->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (priv->domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) irq_domain_remove(priv->domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static const struct of_device_id grgpio_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {.name = "GAISLER_GPIO"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {.name = "01_01a"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_DEVICE_TABLE(of, grgpio_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static struct platform_driver grgpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "grgpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .of_match_table = grgpio_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .probe = grgpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .remove = grgpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) module_platform_driver(grgpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_AUTHOR("Aeroflex Gaisler AB.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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