Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * GPIO driver for the Diamond Systems GPIO-MM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2016 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This driver supports the following Diamond Systems devices: GPIO-MM and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * GPIO-MM-12.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GPIOMM_EXTENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) static unsigned int base[MAX_NUM_GPIOMM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static unsigned int num_gpiomm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * struct gpiomm_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * @chip:	instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * @io_state:	bit I/O state (whether bit is set to input or output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * @out_state:	output bits state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * @control:	Control registers state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @lock:	synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * @base:	base port address of the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct gpiomm_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned char io_state[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	unsigned char out_state[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	unsigned char control[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	const unsigned int port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	const unsigned int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (gpiommgpio->io_state[port] & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static int gpiomm_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	const unsigned int io_port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	const unsigned int control_port = io_port / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	spin_lock_irqsave(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Check if configuring Port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (io_port == 2 || io_port == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		/* Port C can be configured by nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		if (offset % 8 > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			gpiommgpio->io_state[io_port] |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			gpiommgpio->control[control_port] |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			gpiommgpio->io_state[io_port] |= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			gpiommgpio->control[control_port] |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		gpiommgpio->io_state[io_port] |= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (io_port == 0 || io_port == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			gpiommgpio->control[control_port] |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			gpiommgpio->control[control_port] |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	control = BIT(7) | gpiommgpio->control[control_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static int gpiomm_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	const unsigned int io_port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	const unsigned int control_port = io_port / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	const unsigned int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	const unsigned int control_addr = gpiommgpio->base + 3 + control_port*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	spin_lock_irqsave(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* Check if configuring Port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (io_port == 2 || io_port == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		/* Port C can be configured by nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		if (offset % 8 > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			gpiommgpio->io_state[io_port] &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			gpiommgpio->control[control_port] &= ~BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			gpiommgpio->io_state[io_port] &= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			gpiommgpio->control[control_port] &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		gpiommgpio->io_state[io_port] &= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if (io_port == 0 || io_port == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			gpiommgpio->control[control_port] &= ~BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			gpiommgpio->control[control_port] &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		gpiommgpio->out_state[io_port] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		gpiommgpio->out_state[io_port] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	control = BIT(7) | gpiommgpio->control[control_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	outb(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	const unsigned int port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	const unsigned int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	const unsigned int in_port = (port > 2) ? port + 1 : port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned int port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	spin_lock_irqsave(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* ensure that GPIO is set for input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!(gpiommgpio->io_state[port] & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	port_state = inb(gpiommgpio->base + in_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return !!(port_state & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	unsigned int port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	/* clear bits array to a clean slate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bitmap_zero(bits, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		port_addr = gpiommgpio->base + ports[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		port_state = inb(port_addr) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		bitmap_set_value8(bits, port_state, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void gpiomm_gpio_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	const unsigned int port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	const unsigned int mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	const unsigned int out_port = (port > 2) ? port + 1 : port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	spin_lock_irqsave(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		gpiommgpio->out_state[port] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		gpiommgpio->out_state[port] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	outb(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	size_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	unsigned int port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	unsigned long bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		index = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		port_addr = gpiommgpio->base + ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		spin_lock_irqsave(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		/* update output state data and set device gpio register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		gpiommgpio->out_state[index] &= ~gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		gpiommgpio->out_state[index] |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		outb(gpiommgpio->out_state[index], port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		spin_unlock_irqrestore(&gpiommgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GPIOMM_NGPIO 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const char *gpiomm_names[GPIOMM_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	"Port 1A0", "Port 1A1", "Port 1A2", "Port 1A3", "Port 1A4", "Port 1A5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	"Port 1A6", "Port 1A7", "Port 1B0", "Port 1B1", "Port 1B2", "Port 1B3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	"Port 1B4", "Port 1B5", "Port 1B6", "Port 1B7", "Port 1C0", "Port 1C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	"Port 1C2", "Port 1C3", "Port 1C4", "Port 1C5", "Port 1C6", "Port 1C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	"Port 2A0", "Port 2A1", "Port 2A2", "Port 2A3", "Port 2A4", "Port 2A5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	"Port 2A6", "Port 2A7", "Port 2B0", "Port 2B1", "Port 2B2", "Port 2B3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	"Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int gpiomm_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct gpiomm_gpio *gpiommgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	const char *const name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	gpiommgpio = devm_kzalloc(dev, sizeof(*gpiommgpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (!gpiommgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (!devm_request_region(dev, base[id], GPIOMM_EXTENT, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			base[id], base[id] + GPIOMM_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	gpiommgpio->chip.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	gpiommgpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	gpiommgpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	gpiommgpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	gpiommgpio->chip.ngpio = GPIOMM_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	gpiommgpio->chip.names = gpiomm_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	gpiommgpio->chip.get_direction = gpiomm_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	gpiommgpio->chip.direction_input = gpiomm_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	gpiommgpio->chip.direction_output = gpiomm_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	gpiommgpio->chip.get = gpiomm_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	gpiommgpio->chip.get_multiple = gpiomm_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	gpiommgpio->chip.set = gpiomm_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	gpiommgpio->base = base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	spin_lock_init(&gpiommgpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	/* initialize all GPIO as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	outb(0x80, base[id] + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	outb(0x00, base[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	outb(0x00, base[id] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	outb(0x00, base[id] + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	outb(0x80, base[id] + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	outb(0x00, base[id] + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	outb(0x00, base[id] + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	outb(0x00, base[id] + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static struct isa_driver gpiomm_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.probe = gpiomm_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.name = "gpio-mm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) module_isa_driver(gpiomm_driver, num_gpiomm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_DESCRIPTION("Diamond Systems GPIO-MM GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MODULE_LICENSE("GPL v2");