Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Faraday Technolog FTGPIO010 gpiochip and interrupt routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Based on arch/arm/mach-gemini/gpio.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Based on plat-mxc/gpio.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* GPIO registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define GPIO_DATA_OUT		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define GPIO_DATA_IN		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define GPIO_DIR		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define GPIO_BYPASS_IN		0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GPIO_DATA_SET		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GPIO_DATA_CLR		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define GPIO_PULL_EN		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define GPIO_PULL_TYPE		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define GPIO_INT_EN		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define GPIO_INT_STAT_RAW	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GPIO_INT_STAT_MASKED	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPIO_INT_MASK		0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GPIO_INT_CLR		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GPIO_INT_TYPE		0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPIO_INT_BOTH_EDGE	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GPIO_INT_LEVEL		0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define GPIO_DEBOUNCE_EN	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define GPIO_DEBOUNCE_PRESCALE	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * struct ftgpio_gpio - Gemini GPIO state container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * @dev: containing device for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * @gc: gpiochip for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * @irq: irqchip for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  * @base: remapped I/O-memory base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  * @clk: silicon clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct ftgpio_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct irq_chip irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static void ftgpio_gpio_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void ftgpio_gpio_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	val = readl(g->base + GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	val &= ~BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writel(val, g->base + GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) static void ftgpio_gpio_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	val = readl(g->base + GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	val |= BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	writel(val, g->base + GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	u32 mask = BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	u32 reg_both, reg_level, reg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	reg_type = readl(g->base + GPIO_INT_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	reg_level = readl(g->base + GPIO_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		reg_type &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		reg_both |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		reg_type &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		reg_both &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		reg_level &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		reg_type &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		reg_both &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		reg_level |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		reg_type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		reg_level &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		reg_type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		reg_level |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		irq_set_handler_locked(d, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	writel(reg_type, g->base + GPIO_INT_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel(reg_level, g->base + GPIO_INT_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ftgpio_gpio_ack_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void ftgpio_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stat = readl(g->base + GPIO_INT_STAT_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		for_each_set_bit(offset, &stat, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			generic_handle_irq(irq_find_mapping(gc->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 							    offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 				  unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	enum pin_config_param param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32 arg = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned long pclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u32 deb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (param != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	 * Debounce only works if interrupts are enabled. The manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	 * states that if PCLK is 66 MHz, and this is set to 0x7D0, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	 * PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * 2000 decimal, so what they mean is simply that the PCLK is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 * divided by this value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	 * As we get a debounce setting in microseconds, we calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * desired period time and see if we can get a suitable debounce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	pclk_freq = clk_get_rate(g->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	/* This register is only 24 bits wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (deb_div > (1 << 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		deb_div, (pclk_freq/deb_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (val == deb_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		 * The debounce timer happens to already be set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		 * desirable value, what a coincidence! We can just enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		 * debounce on this GPIO line and return. This happens more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 * often than you think, for example when all GPIO keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		 * on a system are requesting the same debounce interval.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		val = readl(g->base + GPIO_DEBOUNCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		val |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		writel(val, g->base + GPIO_DEBOUNCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	val = readl(g->base + GPIO_DEBOUNCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		 * Oh no! Someone is already using the debounce with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		 * another setting than what we need. Bummer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* First come, first serve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Enable debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	val |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	writel(val, g->base + GPIO_DEBOUNCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int ftgpio_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct ftgpio_gpio *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	g->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	g->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (IS_ERR(g->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return PTR_ERR(g->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		return irq ? irq : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	g->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	if (!IS_ERR(g->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		ret = clk_prepare_enable(g->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	} else if (PTR_ERR(g->clk) == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		 * Percolate deferrals, for anything else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		 * just live without the clocking.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return PTR_ERR(g->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	ret = bgpio_init(&g->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			 g->base + GPIO_DATA_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			 g->base + GPIO_DATA_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			 g->base + GPIO_DATA_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			 g->base + GPIO_DIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			 NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		dev_err(dev, "unable to init generic GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		goto dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	g->gc.label = "FTGPIO010";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	g->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	g->gc.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	g->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* ngpio is set by bgpio_init() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* We need a silicon clock to do debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!IS_ERR(g->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		g->gc.set_config = ftgpio_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	g->irq.name = "FTGPIO010";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	g->irq.irq_ack = ftgpio_gpio_ack_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	g->irq.irq_mask = ftgpio_gpio_mask_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	g->irq.irq_unmask = ftgpio_gpio_unmask_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	g->irq.irq_set_type = ftgpio_gpio_set_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	girq = &g->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	girq->chip = &g->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	girq->parent_handler = ftgpio_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		goto dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* Disable, unmask and clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	writel(0x0, g->base + GPIO_INT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	writel(0x0, g->base + GPIO_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	writel(~0x0, g->base + GPIO_INT_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	/* Clear any use of debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	writel(0x0, g->base + GPIO_DEBOUNCE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	ret = devm_gpiochip_add_data(dev, &g->gc, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		goto dis_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	platform_set_drvdata(pdev, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	dev_info(dev, "FTGPIO010 @%p registered\n", g->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dis_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!IS_ERR(g->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		clk_disable_unprepare(g->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int ftgpio_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	struct ftgpio_gpio *g = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (!IS_ERR(g->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		clk_disable_unprepare(g->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const struct of_device_id ftgpio_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		.compatible = "cortina,gemini-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.compatible = "moxa,moxart-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.compatible = "faraday,ftgpio010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct platform_driver ftgpio_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		.name		= "ftgpio010-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		.of_match_table = of_match_ptr(ftgpio_gpio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.probe = ftgpio_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.remove = ftgpio_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) builtin_platform_driver(ftgpio_gpio_driver);