^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for Exar XR17V35X chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EXAR_OFFSET_MPIOLVL_LO 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EXAR_OFFSET_MPIOSEL_LO 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EXAR_OFFSET_MPIOLVL_HI 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EXAR_OFFSET_MPIOSEL_HI 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DRIVER_NAME "gpio_exar"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static DEFINE_IDA(ida_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct exar_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) char name[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int first_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void exar_update(struct gpio_chip *chip, unsigned int reg, int val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mutex_lock(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) temp = readb(exar_gpio->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) temp &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) temp |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) writeb(temp, exar_gpio->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mutex_unlock(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int exar_set_direction(struct gpio_chip *chip, int direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned int addr = (offset + exar_gpio->first_pin) / 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EXAR_OFFSET_MPIOSEL_HI : EXAR_OFFSET_MPIOSEL_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned int bit = (offset + exar_gpio->first_pin) % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) exar_update(chip, addr, direction, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int exar_get(struct gpio_chip *chip, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mutex_lock(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) value = readb(exar_gpio->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mutex_unlock(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static int exar_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned int addr = (offset + exar_gpio->first_pin) / 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) EXAR_OFFSET_MPIOSEL_HI : EXAR_OFFSET_MPIOSEL_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int bit = (offset + exar_gpio->first_pin) % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (exar_get(chip, addr) & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int exar_get_value(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int addr = (offset + exar_gpio->first_pin) / 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXAR_OFFSET_MPIOLVL_HI : EXAR_OFFSET_MPIOLVL_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int bit = (offset + exar_gpio->first_pin) % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return !!(exar_get(chip, addr) & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void exar_set_value(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct exar_gpio_chip *exar_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int addr = (offset + exar_gpio->first_pin) / 8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXAR_OFFSET_MPIOLVL_HI : EXAR_OFFSET_MPIOLVL_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int bit = (offset + exar_gpio->first_pin) % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) exar_update(chip, addr, value, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int exar_direction_output(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) exar_set_value(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return exar_set_direction(chip, 0, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int exar_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return exar_set_direction(chip, 1, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int gpio_exar_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pci_dev *pcidev = to_pci_dev(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct exar_gpio_chip *exar_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 first_pin, ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int index, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The UART driver must have mapped region 0 prior to registering this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * device - use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) p = pcim_iomap_table(pcidev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ret = device_property_read_u32(&pdev->dev, "exar,first-pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &first_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = device_property_read_u32(&pdev->dev, "ngpios", &ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) exar_gpio = devm_kzalloc(&pdev->dev, sizeof(*exar_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!exar_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mutex_init(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) index = ida_simple_get(&ida_index, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (index < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) ret = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto err_mutex_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) sprintf(exar_gpio->name, "exar_gpio%d", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) exar_gpio->gpio_chip.label = exar_gpio->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) exar_gpio->gpio_chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) exar_gpio->gpio_chip.direction_output = exar_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) exar_gpio->gpio_chip.direction_input = exar_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) exar_gpio->gpio_chip.get_direction = exar_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) exar_gpio->gpio_chip.get = exar_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) exar_gpio->gpio_chip.set = exar_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) exar_gpio->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) exar_gpio->gpio_chip.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) exar_gpio->regs = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) exar_gpio->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) exar_gpio->first_pin = first_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = devm_gpiochip_add_data(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &exar_gpio->gpio_chip, exar_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto err_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) platform_set_drvdata(pdev, exar_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) err_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ida_simple_remove(&ida_index, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err_mutex_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mutex_destroy(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int gpio_exar_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct exar_gpio_chip *exar_gpio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ida_simple_remove(&ida_index, exar_gpio->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mutex_destroy(&exar_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static struct platform_driver gpio_exar_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .probe = gpio_exar_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .remove = gpio_exar_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) module_platform_driver(gpio_exar_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_ALIAS("platform:" DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DESCRIPTION("Exar GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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