^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Generic EP93xx GPIO handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Ryan Mallon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on code originally from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * linux/arch/arm/mach-ep93xx/core.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EP93XX_GPIO_F_INT_STATUS 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EP93XX_GPIO_A_INT_STATUS 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EP93XX_GPIO_B_INT_STATUS 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Maximum value for gpio line identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EP93XX_GPIO_LINE_MAX 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Number of GPIO chips in EP93XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EP93XX_GPIO_CHIP_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Maximum value for irq capable line identifiers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EP93XX_GPIO_LINE_MAX_IRQ 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Static mapping of GPIO bank F IRQS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * F0..F7 (16..24) to irq 80..87.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EP93XX_GPIO_F_IRQ_BASE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct ep93xx_gpio_irq_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct irq_chip ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 irq_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u8 int_unmasked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 int_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 int_type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u8 int_type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 int_debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct ep93xx_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct ep93xx_gpio_irq_chip *eic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct ep93xx_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return egc->eic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Interrupt handling for EP93xx on-chip GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EP93XX_INT_TYPE1_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EP93XX_INT_TYPE2_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EP93XX_INT_EOI_OFFSET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EP93XX_INT_EN_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EP93XX_INT_STATUS_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EP93XX_INT_RAW_STATUS_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EP93XX_INT_DEBOUNCE_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ep93xx_gpio_irq_chip *eic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writeb_relaxed(eic->int_type2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writeb_relaxed(eic->int_type1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb_relaxed(eic->int_unmasked & eic->int_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int offset, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int port_mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) eic->int_debounce |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) eic->int_debounce &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writeb(eic->int_debounce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Dispatch the IRQs to the irqdomain of each A and B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * gpiochip irqdomains depending on what has fired.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * The tricky part is that the IRQ line is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * between bank A and B and each has their own gpiochip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for_each_set_bit(offset, &stat, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for_each_set_bit(offset, &stat, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * map discontiguous hw irq range to continuous sw irq range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) generic_handle_irq(gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void ep93xx_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int port_mask = BIT(d->irq & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) eic->int_type2 ^= port_mask; /* switch edge direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ep93xx_gpio_update_int_params(epg, eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int port_mask = BIT(d->irq & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) eic->int_type2 ^= port_mask; /* switch edge direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) eic->int_unmasked &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ep93xx_gpio_update_int_params(epg, eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void ep93xx_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) eic->int_unmasked &= ~BIT(d->irq & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ep93xx_gpio_update_int_params(epg, eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void ep93xx_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) eic->int_unmasked |= BIT(d->irq & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ep93xx_gpio_update_int_params(epg, eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * gpio_int_type1 controls whether the interrupt is level (0) or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * edge (1) triggered, while gpio_int_type2 controls whether it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * triggers on low/falling (0) or high/rising (1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct ep93xx_gpio *epg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int offset = d->irq & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int port_mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) irq_flow_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) gc->direction_input(gc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) eic->int_type1 |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) eic->int_type2 |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) eic->int_type1 |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) eic->int_type2 &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) eic->int_type1 &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) eic->int_type2 |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) eic->int_type1 &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) eic->int_type2 &= ~port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) eic->int_type1 |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* set initial polarity based on current input level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (gc->get(gc, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) eic->int_type2 &= ~port_mask; /* falling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) eic->int_type2 |= port_mask; /* rising */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) irq_set_handler_locked(d, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) eic->int_enabled |= port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ep93xx_gpio_update_int_params(epg, eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*************************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * gpiolib interface for EP93xx on-chip GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct ep93xx_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bool has_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) bool has_hierarchical_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .label = _label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .data = _data, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .dir = _dir, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .irq = _irq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .base = _base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .has_irq = _has_irq, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .has_hierarchical_irq = _has_hier, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .irq_base = _irq_base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Bank A has 8 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Bank B has 8 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Bank F has 8 IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return EP93XX_GPIO_F_IRQ_BASE + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ic->irq_ack = ep93xx_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ic->irq_mask = ep93xx_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ic->irq_unmask = ep93xx_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ic->irq_set_type = ep93xx_gpio_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct ep93xx_gpio *epg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct ep93xx_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *data = epg->base + bank->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void __iomem *dir = epg->base + bank->dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct gpio_chip *gc = &egc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) gc->label = bank->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) gc->base = bank->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (bank->has_irq || bank->has_hierarchical_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct irq_chip *ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) gc->set_config = ep93xx_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) egc->eic = devm_kcalloc(dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) sizeof(*egc->eic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (!egc->eic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) egc->eic->irq_offset = bank->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ic = &egc->eic->ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (!ic->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ep93xx_init_irq_chip(dev, ic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) girq->chip = ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (bank->has_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int ab_parent_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) girq->parent_handler = ep93xx_gpio_ab_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) girq->parents = devm_kcalloc(dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) girq->parents[0] = ab_parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) girq->first = bank->irq_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Only bank F has especially funky IRQ handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (bank->has_hierarchical_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int gpio_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * FIXME: convert this to use hierarchical IRQ support!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * this requires fixing the root irqchip to be hierarchial.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) girq->parent_handler = ep93xx_gpio_f_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) girq->num_parents = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) girq->parents = devm_kcalloc(dev, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Pick resources 1..8 for these IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (i = 1; i <= 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) girq->parents[i - 1] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) irq_set_chip_data(gpio_irq, &epg->gc[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) irq_set_chip_and_handler(gpio_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) girq->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) gc->to_irq = ep93xx_gpio_f_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return devm_gpiochip_add_data(dev, gc, epg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int ep93xx_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct ep93xx_gpio *epg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!epg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) epg->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (IS_ERR(epg->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return PTR_ERR(epg->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct ep93xx_gpio_chip *gc = &epg->gc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) bank->label);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct platform_driver ep93xx_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "gpio-ep93xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .probe = ep93xx_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int __init ep93xx_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return platform_driver_register(&ep93xx_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) postcore_initcall(ep93xx_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "H Hartley Sweeten <hsweeten@visionengravers.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MODULE_DESCRIPTION("EP93XX GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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