^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Emma Mobile GPIO Support - GIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct em_gio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *base0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *base1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t sense_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GIO_E1 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GIO_E0 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GIO_EM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GIO_OL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GIO_OH 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GIO_I 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GIO_IIA 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GIO_IEN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GIO_IDS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GIO_IIM 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GIO_RAW 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GIO_MST 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GIO_IIR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GIO_IDT0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GIO_IDT1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GIO_IDT2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GIO_IDT3 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GIO_RAWBL 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GIO_RAWBH 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GIO_IRBL 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GIO_IRBH 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (offs < GIO_IDT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return ioread32(p->base0 + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ioread32(p->base1 + (offs - GIO_IDT0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void em_gio_write(struct em_gio_priv *p, int offs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (offs < GIO_IDT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) iowrite32(value, p->base0 + offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite32(value, p->base1 + (offs - GIO_IDT0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void em_gio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void em_gio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int em_gio_irq_reqres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(p->gpio_chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) "unable to lock HW IRQ %lu for IRQ\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void em_gio_irq_relres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GIO_ASYNC(x) (x + 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int reg, offset, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* 8 x 4 bit fields in 4 IDT registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) reg = GIO_IDT(offset >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) shift = (offset & 0x07) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spin_lock_irqsave(&p->sense_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* disable the interrupt in IIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tmp = em_gio_read(p, GIO_IIA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) tmp &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) em_gio_write(p, GIO_IIA, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* change the sense setting in IDT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) tmp = em_gio_read(p, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp &= ~(0xf << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tmp |= value << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) em_gio_write(p, reg, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* clear pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) em_gio_write(p, GIO_IIR, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* enable the interrupt in IIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tmp = em_gio_read(p, GIO_IIA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) tmp |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) em_gio_write(p, GIO_IIA, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) spin_unlock_irqrestore(&p->sense_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct em_gio_priv *p = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int offset, irqs_handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) while ((pending = em_gio_read(p, GIO_MST))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) offset = __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) em_gio_write(p, GIO_IIR, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) irqs_handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int em_gio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned shift, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* upper 16 bits contains mask and lower 16 actual value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) em_gio_write(gpio_to_priv(chip), reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (BIT(shift + 16)) | (value << shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* output is split into two registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) __em_gio_set(chip, GIO_OL, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) __em_gio_set(chip, GIO_OH, offset - 16, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* write GPIO value to output before selecting output mode of pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) em_gio_set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int em_gio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return pinctrl_gpio_request(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void em_gio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pinctrl_gpio_free(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Set the GPIO as an input to ensure that the next GPIO request won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * drive the GPIO pin as an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) em_gio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct em_gio_priv *p = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) irq_set_chip_data(irq, h->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct irq_domain_ops em_gio_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .map = em_gio_irq_domain_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void em_gio_irq_domain_remove(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct irq_domain *domain = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) irq_domain_remove(domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int em_gio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct em_gio_priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct gpio_chip *gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) const char *name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned int ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int irq[2], ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) p->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) platform_set_drvdata(pdev, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) spin_lock_init(&p->sense_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) irq[0] = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (irq[0] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) irq[1] = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (irq[1] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return irq[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) p->base0 = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (IS_ERR(p->base0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return PTR_ERR(p->base0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) p->base1 = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (IS_ERR(p->base1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return PTR_ERR(p->base1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_err(dev, "Missing ngpios OF property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) gpio_chip = &p->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) gpio_chip->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpio_chip->direction_input = em_gio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) gpio_chip->get = em_gio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) gpio_chip->direction_output = em_gio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) gpio_chip->set = em_gio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gpio_chip->to_irq = em_gio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gpio_chip->request = em_gio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) gpio_chip->free = em_gio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) gpio_chip->label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gpio_chip->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) gpio_chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gpio_chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) gpio_chip->ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) irq_chip = &p->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) irq_chip->name = "gpio-em";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) irq_chip->irq_mask = em_gio_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) irq_chip->irq_unmask = em_gio_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) irq_chip->irq_set_type = em_gio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) irq_chip->irq_request_resources = em_gio_irq_reqres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) irq_chip->irq_release_resources = em_gio_irq_relres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) p->irq_domain = irq_domain_add_simple(dev->of_node, ngpios, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) &em_gio_irq_domain_ops, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!p->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev_err(dev, "cannot initialize irq domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = devm_add_action_or_reset(dev, em_gio_irq_domain_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) p->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (devm_request_irq(dev, irq[0], em_gio_irq_handler, 0, name, p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_err(dev, "failed to request low IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (devm_request_irq(dev, irq[1], em_gio_irq_handler, 0, name, p)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(dev, "failed to request high IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ret = devm_gpiochip_add_data(dev, gpio_chip, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) dev_err(dev, "failed to add GPIO controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct of_device_id em_gio_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .compatible = "renesas,em-gio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct platform_driver em_gio_device_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .probe = em_gio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "em_gio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .of_match_table = em_gio_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int __init em_gio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return platform_driver_register(&em_gio_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) postcore_initcall(em_gio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void __exit em_gio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) platform_driver_unregister(&em_gio_device_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_exit(em_gio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MODULE_AUTHOR("Magnus Damm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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