^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2018 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* EIC registers definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPRD_EIC_DBNC_DATA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPRD_EIC_DBNC_DMSK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPRD_EIC_DBNC_IEV 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPRD_EIC_DBNC_IE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SPRD_EIC_DBNC_RIS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPRD_EIC_DBNC_MIS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPRD_EIC_DBNC_IC 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPRD_EIC_DBNC_TRIG 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPRD_EIC_DBNC_CTRL0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPRD_EIC_LATCH_INTEN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPRD_EIC_LATCH_INTRAW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPRD_EIC_LATCH_INTMSK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPRD_EIC_LATCH_INTCLR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPRD_EIC_LATCH_INTPOL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPRD_EIC_LATCH_INTMODE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPRD_EIC_ASYNC_INTIE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPRD_EIC_ASYNC_INTRAW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPRD_EIC_ASYNC_INTMSK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPRD_EIC_ASYNC_INTCLR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPRD_EIC_ASYNC_INTMODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPRD_EIC_ASYNC_INTBOTH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPRD_EIC_ASYNC_INTPOL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPRD_EIC_ASYNC_DATA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SPRD_EIC_SYNC_INTIE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPRD_EIC_SYNC_INTRAW 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPRD_EIC_SYNC_INTMSK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPRD_EIC_SYNC_INTCLR 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPRD_EIC_SYNC_INTMODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPRD_EIC_SYNC_INTBOTH 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPRD_EIC_SYNC_INTPOL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPRD_EIC_SYNC_DATA 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * The digital-chip EIC controller can support maximum 3 banks, and each bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * contains 8 EICs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPRD_EIC_MAX_BANK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPRD_EIC_PER_BANK_NR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRD_EIC_DATA_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRD_EIC_DBNC_MASK GENMASK(11, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The Spreadtrum EIC (external interrupt controller) can be used only in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * input mode to generate interrupts if detecting input signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * debounce EIC, latch EIC, async EIC and sync EIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * The debounce EIC is used to capture the input signals' stable status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * (millisecond resolution) and a single-trigger mechanism is introduced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * into this sub-module to enhance the input event detection reliability.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * The debounce range is from 1ms to 4s with a step size of 1ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * The latch EIC is used to latch some special power down signals and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * generate interrupts, since the latch EIC does not depend on the APB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * to capture signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * The async EIC uses a 32k clock to capture the short signals (microsecond
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * resolution) to generate interrupts by level or edge trigger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * The EIC-sync is similar with GPIO's input function, which is a synchronized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * signal input register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum sprd_eic_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) SPRD_EIC_DEBOUNCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) SPRD_EIC_LATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) SPRD_EIC_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) SPRD_EIC_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) SPRD_EIC_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct sprd_eic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct irq_chip intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) void __iomem *base[SPRD_EIC_MAX_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum sprd_eic_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sprd_eic_variant_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum sprd_eic_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 num_eics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "eic-debounce", "eic-latch", "eic-async",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "eic-sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .type = SPRD_EIC_DEBOUNCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .num_eics = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .type = SPRD_EIC_LATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .num_eics = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct sprd_eic_variant_data sc9860_eic_async_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .type = SPRD_EIC_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .num_eics = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .type = SPRD_EIC_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .num_eics = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (bank >= SPRD_EIC_MAX_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return sprd_eic->base[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) void __iomem *base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spin_lock_irqsave(&sprd_eic->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) tmp = readl_relaxed(base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) tmp |= BIT(SPRD_EIC_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tmp &= ~BIT(SPRD_EIC_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) writel_relaxed(tmp, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) spin_unlock_irqrestore(&sprd_eic->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* EICs are always input, nothing need to do here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* EICs are always input, nothing need to do here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void __iomem *base =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(value, base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long param = pinconf_to_config_param(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 arg = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (param == PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return sprd_eic_set_debounce(chip, offset, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void sprd_eic_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(chip->parent, "Unsupported EIC type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void sprd_eic_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(chip->parent, "Unsupported EIC type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void sprd_eic_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev_err(chip->parent, "Unsupported EIC type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) state = sprd_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) sprd_eic_update(chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) SPRD_EIC_DBNC_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sprd_eic_update(chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SPRD_EIC_DBNC_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) state = sprd_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) sprd_eic_update(chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SPRD_EIC_LATCH_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) sprd_eic_update(chip, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SPRD_EIC_LATCH_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) irq_set_handler_locked(data, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) irq_set_handler_locked(data, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(chip->parent, "Unsupported EIC type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct irq_data *data = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) u32 trigger = irqd_get_trigger_type(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int state, post_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * The debounce EIC and latch EIC can only support level trigger, so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * can toggle the level trigger to emulate the edge trigger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) sprd_eic->type != SPRD_EIC_LATCH) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) !(trigger & IRQ_TYPE_EDGE_BOTH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) sprd_eic_irq_mask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) state = sprd_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) sprd_eic_irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) post_state = sprd_eic_get(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (state != post_state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev_warn(chip->parent, "EIC level was changed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) state = post_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sprd_eic_irq_unmask(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) enum sprd_eic_type type = *(enum sprd_eic_type *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return !strcmp(chip->label, sprd_eic_label_name[type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static void sprd_eic_handle_one_type(struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 bank, n, girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) SPRD_EIC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SPRD_EIC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SPRD_EIC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SPRD_EIC_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev_err(chip->parent, "Unsupported EIC type.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 offset = bank * SPRD_EIC_PER_BANK_NR + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) girq = irq_find_mapping(chip->irq.domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) generic_handle_irq(girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) sprd_eic_toggle_trigger(chip, girq, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void sprd_eic_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct irq_chip *ic = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) enum sprd_eic_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) chained_irq_enter(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * and sync) share one same interrupt line, we should iterate each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * EIC module to check if there are EIC interrupts were triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sprd_eic_handle_one_type(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) chained_irq_exit(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int sprd_eic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct sprd_eic_variant_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct sprd_eic *sprd_eic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dev_err(&pdev->dev, "No matching driver data found.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!sprd_eic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) spin_lock_init(&sprd_eic->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) sprd_eic->type = pdata->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) sprd_eic->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (sprd_eic->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return sprd_eic->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * We can have maximum 3 banks EICs, and each EIC has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * its own base address. But some platform maybe only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * have one bank EIC, thus base[1] and base[2] can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) res = platform_get_resource(pdev, IORESOURCE_MEM, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (IS_ERR(sprd_eic->base[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return PTR_ERR(sprd_eic->base[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) sprd_eic->chip.ngpio = pdata->num_eics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) sprd_eic->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) sprd_eic->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) sprd_eic->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) sprd_eic->chip.direction_input = sprd_eic_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) switch (sprd_eic->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case SPRD_EIC_DEBOUNCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) sprd_eic->chip.request = sprd_eic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) sprd_eic->chip.free = sprd_eic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) sprd_eic->chip.set_config = sprd_eic_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) sprd_eic->chip.set = sprd_eic_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case SPRD_EIC_ASYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case SPRD_EIC_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) sprd_eic->chip.get = sprd_eic_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) case SPRD_EIC_LATCH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) sprd_eic->intc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) irq = &sprd_eic->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) irq->chip = &sprd_eic->intc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) irq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) irq->parent_handler = sprd_eic_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) irq->parent_handler_data = sprd_eic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) irq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) irq->parents = &sprd_eic->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) platform_set_drvdata(pdev, sprd_eic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct of_device_id sprd_eic_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .compatible = "sprd,sc9860-eic-debounce",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .data = &sc9860_eic_dbnc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .compatible = "sprd,sc9860-eic-latch",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .data = &sc9860_eic_latch_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .compatible = "sprd,sc9860-eic-async",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .data = &sc9860_eic_async_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .compatible = "sprd,sc9860-eic-sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .data = &sc9860_eic_sync_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* end of list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static struct platform_driver sprd_eic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .probe = sprd_eic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .name = "sprd-eic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .of_match_table = sprd_eic_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) module_platform_driver(sprd_eic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MODULE_DESCRIPTION("Spreadtrum EIC driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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