^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011 Jamie Iles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All enquiries to support@picochip.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/gpio-dwapb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "gpiolib.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "gpiolib-acpi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIO_SWPORTA_DR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPIO_SWPORTA_DDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPIO_SWPORTB_DR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_SWPORTB_DDR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPIO_SWPORTC_DR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPIO_SWPORTC_DDR 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO_SWPORTD_DR 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPIO_SWPORTD_DDR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPIO_INTEN 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPIO_INTMASK 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO_INTTYPE_LEVEL 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_INT_POLARITY 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_INTSTATUS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_PORTA_DEBOUNCE 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_PORTA_EOI 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_EXT_PORTA 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_EXT_PORTB 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_EXT_PORTC 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_EXT_PORTD 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DWAPB_DRIVER_NAME "gpio-dwapb"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DWAPB_MAX_PORTS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_REG_OFFSET_V2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPIO_INTMASK_V2 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_INTTYPE_LEVEL_V2 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPIO_INT_POLARITY_V2 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPIO_INTSTATUS_V2 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPIO_PORTA_EOI_V2 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DWAPB_NR_CLOCKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dwapb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Store GPIO context across system-wide suspend/resume transitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct dwapb_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 ext;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 int_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 int_deb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 wake_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct dwapb_gpio_port_irqchip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int irq[DWAPB_MAX_GPIOS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dwapb_gpio_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dwapb_gpio_port_irqchip *pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dwapb_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct dwapb_context *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define to_dwapb_gpio(_gc) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct dwapb_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dwapb_gpio_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int nr_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk_bulk_data clks[DWAPB_NR_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline u32 gpio_reg_v2_convert(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) switch (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) case GPIO_INTMASK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return GPIO_INTMASK_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case GPIO_INTTYPE_LEVEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return GPIO_INTTYPE_LEVEL_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) case GPIO_INT_POLARITY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return GPIO_INT_POLARITY_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case GPIO_INTSTATUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return GPIO_INTSTATUS_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) case GPIO_PORTA_EOI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return GPIO_PORTA_EOI_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (gpio->flags & GPIO_REG_OFFSET_V2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return gpio_reg_v2_convert(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_chip *gc = &gpio->ports[0].gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void __iomem *reg_base = gpio->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_chip *gc = &gpio->ports[0].gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void __iomem *reg_base = gpio->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct dwapb_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) for (i = 0; i < gpio->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) port = &gpio->ports[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (port->idx == offs / DWAPB_MAX_GPIOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) gc = &port->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pol = dwapb_read(gpio, GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Just read the current value right out of the data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) pol &= ~BIT(offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pol |= BIT(offs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dwapb_write(gpio, GPIO_INT_POLARITY, pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct gpio_chip *gc = &gpio->ports[0].gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 irq_type = irq_get_trigger_type(gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) generic_handle_irq(gpio_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dwapb_toggle_trigger(gpio, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void dwapb_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dwapb_do_irq(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return IRQ_RETVAL(dwapb_do_irq(dev_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static void dwapb_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 val = BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dwapb_write(gpio, GPIO_PORTA_EOI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void dwapb_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dwapb_write(gpio, GPIO_INTMASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void dwapb_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dwapb_write(gpio, GPIO_INTMASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void dwapb_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val = dwapb_read(gpio, GPIO_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) val |= BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dwapb_write(gpio, GPIO_INTEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void dwapb_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) val = dwapb_read(gpio, GPIO_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val &= ~BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dwapb_write(gpio, GPIO_INTEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static int dwapb_irq_set_type(struct irq_data *d, u32 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) irq_hw_number_t bit = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned long level, polarity, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (type & ~IRQ_TYPE_SENSE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) level |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dwapb_toggle_trigger(gpio, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) level |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) polarity |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) level |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) polarity &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) level &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) polarity |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) level &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) polarity &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (type & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) else if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (type != IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct dwapb_context *ctx = gpio->ports[0].ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_hw_number_t bit = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ctx->wake_en |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ctx->wake_en &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned offset, unsigned debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct dwapb_gpio_port *port = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct dwapb_gpio *gpio = port->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long flags, val_deb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val_deb |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) val_deb &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return dwapb_gpio_set_debounce(gc, offset, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct dwapb_port_property *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Group all available IRQs into an array of parental IRQs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for (i = 0; i < pp->ngpio; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!pp->irq[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pirq->irq[pirq->nr_irqs++] = pp->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return pirq->nr_irqs ? 0 : -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct dwapb_gpio_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct dwapb_port_property *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dwapb_gpio_port_irqchip *pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct gpio_chip *gc = &port->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!pirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (dwapb_convert_irqs(pirq, pp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) goto err_kfree_pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) girq = &gc->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) port->pirq = pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pirq->irqchip.name = DWAPB_DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pirq->irqchip.irq_ack = dwapb_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) pirq->irqchip.irq_mask = dwapb_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pirq->irqchip.irq_unmask = dwapb_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) pirq->irqchip.irq_set_type = dwapb_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pirq->irqchip.irq_enable = dwapb_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pirq->irqchip.irq_disable = dwapb_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pirq->irqchip.irq_set_wake = dwapb_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!pp->irq_shared) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) girq->num_parents = pirq->nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) girq->parents = pirq->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) girq->parent_handler_data = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) girq->parent_handler = dwapb_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * Request a shared IRQ since where MFD would have devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * using the same irq pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) err = devm_request_irq(gpio->dev, pp->irq[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dwapb_irq_handler_mfd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev_err(gpio->dev, "error requesting IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto err_kfree_pirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) girq->chip = &pirq->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) err_kfree_pirq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) devm_kfree(gpio->dev, pirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct dwapb_port_property *pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) unsigned int offs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct dwapb_gpio_port *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) void __iomem *dat, *set, *dirout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) port = &gpio->ports[offs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) port->gpio = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) port->idx = pp->idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (!port->ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* This registers 32 GPIO lines per port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) port->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) port->gc.of_node = to_of_node(pp->fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) port->gc.ngpio = pp->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) port->gc.base = pp->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Only port A support debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (pp->idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) port->gc.set_config = dwapb_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Only port A can provide interrupts in all configurations of the IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (pp->idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dwapb_configure_irqs(gpio, port, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) port->idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct dwapb_port_property *pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int irq = -ENXIO, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (fwnode_property_read_bool(fwnode, "interrupt-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) np = to_of_node(fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) for (j = 0; j < pp->ngpio; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) irq = of_irq_get(np, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) else if (has_acpi_companion(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) irq = platform_get_irq_optional(to_platform_device(dev), j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pp->irq[j] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct dwapb_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct dwapb_port_property *pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) int nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) nports = device_get_child_node_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (nports == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!pdata->properties)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pdata->nports = nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) device_for_each_child_node(dev, fwnode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pp = &pdata->properties[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) pp->fwnode = fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) pp->idx >= DWAPB_MAX_PORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "missing/invalid port index for port%d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) fwnode_handle_put(fwnode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_info(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "failed to get number of gpios for port%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) pp->ngpio = DWAPB_MAX_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pp->irq_shared = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pp->gpio_base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * Only port A can provide interrupts in all configurations of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * the IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (pp->idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dwapb_get_irq(dev, fwnode, pp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static void dwapb_assert_reset(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct dwapb_gpio *gpio = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) reset_control_assert(gpio->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int dwapb_get_reset(struct dwapb_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (IS_ERR(gpio->rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_err(gpio->dev, "Cannot get reset descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return PTR_ERR(gpio->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err = reset_control_deassert(gpio->rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(gpio->dev, "Cannot deassert reset lane\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void dwapb_disable_clks(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct dwapb_gpio *gpio = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int dwapb_get_clks(struct dwapb_gpio *gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* Optional bus and debounce clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) gpio->clks[0].id = "bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) gpio->clks[1].id = "db";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gpio->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct of_device_id dwapb_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { .compatible = "snps,dw-apb-gpio", .data = (void *)0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { /* Sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MODULE_DEVICE_TABLE(of, dwapb_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const struct acpi_device_id dwapb_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {"HISI0181", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {"APMC0D07", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {"APMC0D81", GPIO_REG_OFFSET_V2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int dwapb_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct dwapb_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct dwapb_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) pdata = dwapb_gpio_get_pdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (!pdata->nports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) gpio->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) gpio->nr_ports = pdata->nports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) err = dwapb_get_reset(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sizeof(*gpio->ports), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (!gpio->ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) gpio->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (IS_ERR(gpio->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return PTR_ERR(gpio->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) err = dwapb_get_clks(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) gpio->flags = (uintptr_t)device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for (i = 0; i < gpio->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int dwapb_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct dwapb_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct gpio_chip *gc = &gpio->ports[0].gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) for (i = 0; i < gpio->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned int idx = gpio->ports[i].idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct dwapb_context *ctx = gpio->ports[i].ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ctx->dir = dwapb_read(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ctx->data = dwapb_read(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ctx->ext = dwapb_read(gpio, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Only port A can provide interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Mask out interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int dwapb_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct dwapb_gpio *gpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct gpio_chip *gc = &gpio->ports[0].gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) for (i = 0; i < gpio->nr_ports; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) unsigned int idx = gpio->ports[i].idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct dwapb_context *ctx = gpio->ports[i].ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dwapb_write(gpio, offset, ctx->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dwapb_write(gpio, offset, ctx->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) dwapb_write(gpio, offset, ctx->ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Only port A can provide interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* Clear out spurious interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dwapb_gpio_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static struct platform_driver dwapb_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .name = DWAPB_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .pm = &dwapb_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .of_match_table = dwapb_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .acpi_match_table = dwapb_acpi_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .probe = dwapb_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) module_platform_driver(dwapb_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_AUTHOR("Jamie Iles");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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