^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the Diolan DLN-2 USB-GPIO adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/dln2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DLN2_GPIO_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DLN2_GPIO_EVENT_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DLN2_GPIO_EVENT_CHANGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DLN2_GPIO_EVENT_LVL_HIGH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DLN2_GPIO_EVENT_LVL_LOW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DLN2_GPIO_EVENT_MASK 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DLN2_GPIO_MAX_PINS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct dln2_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct irq_chip irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Cache pin direction to save us one transfer, since the hardware has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * separate commands to read the in and out values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* active IRQs - not synced to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* active IRQS - synced to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int irq_type[DLN2_GPIO_MAX_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct dln2_gpio_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __le16 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct dln2_gpio_pin_val {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __le16 pin __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int dln2_gpio_get_pin_count(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __le16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int len = sizeof(count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (len < sizeof(count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return le16_to_cpu(count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dln2_gpio_pin req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pin = cpu_to_le16(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct dln2_gpio_pin req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pin = cpu_to_le16(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct dln2_gpio_pin_val rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int len = sizeof(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (len < sizeof(rsp) || req.pin != rsp.pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return rsp.value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return !!ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return !!ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int pin, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct dln2_gpio_pin_val req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .pin = cpu_to_le16(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .value = value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define DLN2_GPIO_DIRECTION_IN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DLN2_GPIO_DIRECTION_OUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct dln2_gpio_pin req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .pin = cpu_to_le16(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct dln2_gpio_pin_val rsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int len = sizeof(rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* cache the pin direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) &req, sizeof(req), &rsp, &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (len < sizeof(rsp) || req.pin != rsp.pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) switch (rsp.value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) case DLN2_GPIO_DIRECTION_IN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clear_bit(offset, dln2->output_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) case DLN2_GPIO_DIRECTION_OUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) set_bit(offset, dln2->output_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = -EPROTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (test_bit(offset, dln2->output_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dir = dln2_gpio_get_direction(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (dir < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (dir == GPIO_LINE_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return dln2_gpio_pin_get_in_val(dln2, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return dln2_gpio_pin_get_out_val(dln2, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dln2_gpio_pin_set_out_val(dln2, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct dln2_gpio_pin_val req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .pin = cpu_to_le16(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .value = dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) &req, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (dir == DLN2_GPIO_DIRECTION_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) set_bit(offset, dln2->output_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) clear_bit(offset, dln2->output_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = dln2_gpio_pin_set_out_val(dln2, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct dln2_gpio *dln2 = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __le32 duration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) duration = cpu_to_le32(pinconf_to_config_argument(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &duration, sizeof(duration));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned type, unsigned period)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) __le16 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __le16 period;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) } __packed req = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .pin = cpu_to_le16(pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .type = type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .period = cpu_to_le16(period),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) &req, sizeof(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void dln2_irq_unmask(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct dln2_gpio *dln2 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int pin = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) set_bit(pin, dln2->unmasked_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void dln2_irq_mask(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dln2_gpio *dln2 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int pin = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) clear_bit(pin, dln2->unmasked_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int dln2_irq_set_type(struct irq_data *irqd, unsigned type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct dln2_gpio *dln2 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int pin = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void dln2_irq_bus_lock(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct dln2_gpio *dln2 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mutex_lock(&dln2->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void dln2_irq_bus_unlock(struct irq_data *irqd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dln2_gpio *dln2 = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int pin = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int enabled, unmasked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enabled = test_bit(pin, dln2->enabled_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) unmasked = test_bit(pin, dln2->unmasked_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (enabled != unmasked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (unmasked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) set_bit(pin, dln2->enabled_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) type = DLN2_GPIO_EVENT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clear_bit(pin, dln2->enabled_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_err(dln2->gpio.parent, "failed to set event\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mutex_unlock(&dln2->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void dln2_gpio_event(struct platform_device *pdev, u16 echo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) const void *data, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int pin, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __le16 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __le16 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } __packed *event = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct dln2_gpio *dln2 = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (len < sizeof(*event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dln2->gpio.parent, "short event message\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) pin = le16_to_cpu(event->pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (pin >= dln2->gpio.ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) irq = irq_find_mapping(dln2->gpio.irq.domain, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) switch (dln2->irq_type[pin]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case DLN2_GPIO_EVENT_CHANGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (event->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case DLN2_GPIO_EVENT_CHANGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!event->value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int dln2_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct dln2_gpio *dln2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pins = dln2_gpio_get_pin_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (pins < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dev_err(dev, "failed to get pin count: %d\n", pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (pins > DLN2_GPIO_MAX_PINS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pins = DLN2_GPIO_MAX_PINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!dln2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mutex_init(&dln2->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dln2->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dln2->gpio.label = "dln2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dln2->gpio.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dln2->gpio.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dln2->gpio.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dln2->gpio.ngpio = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dln2->gpio.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dln2->gpio.set = dln2_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dln2->gpio.get = dln2_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dln2->gpio.request = dln2_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dln2->gpio.free = dln2_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dln2->gpio.get_direction = dln2_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dln2->gpio.direction_input = dln2_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dln2->gpio.direction_output = dln2_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dln2->gpio.set_config = dln2_gpio_set_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dln2->irqchip.name = "dln2-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dln2->irqchip.irq_mask = dln2_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dln2->irqchip.irq_unmask = dln2_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dln2->irqchip.irq_set_type = dln2_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dln2->irqchip.irq_bus_lock = dln2_irq_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dln2->irqchip.irq_bus_sync_unlock = dln2_irq_bus_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) girq = &dln2->gpio.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) girq->chip = &dln2->irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* The event comes from the outside so no parent handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) platform_set_drvdata(pdev, dln2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(dev, "failed to add gpio chip: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) dln2_gpio_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_err(dev, "failed to register event cb: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int dln2_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static struct platform_driver dln2_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .driver.name = "dln2-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .probe = dln2_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .remove = dln2_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) module_platform_driver(dln2_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MODULE_ALIAS("platform:dln2-gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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