^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI DaVinci GPIO Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006-2007 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_data/gpio-davinci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm-generic/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MAX_REGS_BANKS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MAX_INT_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct davinci_gpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 out_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 set_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 clr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 in_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 set_rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 clr_rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 set_falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 clr_falling;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static void __iomem *gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct davinci_gpio_irq_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct davinci_gpio_controller *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct davinci_gpio_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Serialize access to GPIO registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void __iomem *regs[MAX_REGS_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int irqs[MAX_INT_PER_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline u32 __gpio_mask(unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return 1 << (gpio % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int davinci_gpio_irq_setup(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int __davinci_direction(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned offset, bool out, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct davinci_gpio_controller *d = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int bank = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 mask = __gpio_mask(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) g = d->regs[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_lock_irqsave(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) temp = readl_relaxed(&g->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) temp &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) temp |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) writel_relaxed(temp, &g->dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_unlock_irqrestore(&d->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return __davinci_direction(chip, offset, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return __davinci_direction(chip, offset, true, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Read the pin's value (works even if it's set up as output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * returns zero/nonzero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * Note that changes are synched to the GPIO clock, so reading values back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * right after you've set them may give old values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct davinci_gpio_controller *d = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int bank = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) g = d->regs[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Assuming the pin is muxed as a gpio output, set its output value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct davinci_gpio_controller *d = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int bank = offset / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) g = d->regs[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) writel_relaxed(__gpio_mask(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) value ? &g->set_data : &g->clr_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static struct davinci_gpio_platform_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) davinci_gpio_get_pdata(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct device_node *dn = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct davinci_gpio_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = of_property_read_u32(dn, "ti,ngpio", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) goto of_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pdata->ngpio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) goto of_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) pdata->gpio_unbanked = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) of_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static int davinci_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int bank, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned int ngpio, nbank, nirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct davinci_gpio_controller *chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct davinci_gpio_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pdata = davinci_gpio_get_pdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "No platform data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev->platform_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * The gpio banks conceptually expose a segmented bitmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * and "ngpio" is one more than the largest zero-based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * bit index that's valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ngpio = pdata->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ngpio == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(dev, "How many GPIOs?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (WARN_ON(ARCH_NR_GPIOS < ngpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ngpio = ARCH_NR_GPIOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * If there are unbanked interrupts then the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * interrupts is equal to number of gpios else all are banked so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * number of interrupts is equal to number of banks(each with 16 gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (pdata->gpio_unbanked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) nirq = pdata->gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) nirq = DIV_ROUND_UP(ngpio, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!chips)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gpio_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (IS_ERR(gpio_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return PTR_ERR(gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) for (i = 0; i < nirq; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) chips->irqs[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (chips->irqs[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) chips->chip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) chips->chip.direction_input = davinci_direction_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) chips->chip.get = davinci_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) chips->chip.direction_output = davinci_direction_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) chips->chip.set = davinci_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) chips->chip.ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_OF_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) chips->chip.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) chips->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) chips->chip.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) chips->chip.request = gpiochip_generic_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) chips->chip.free = gpiochip_generic_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) spin_lock_init(&chips->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) nbank = DIV_ROUND_UP(ngpio, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) for (bank = 0; bank < nbank; bank++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) chips->regs[bank] = gpio_base + offset_array[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) platform_set_drvdata(pdev, chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = davinci_gpio_irq_setup(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*--------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * We expect irqs will normally be set up as input pins, but they can also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * used as output pins ... which is convenient for testing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * NOTE: The first few GPIOs also have direct INTC hookups in addition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * to their GPIOBNK0 irq, with a bit less overhead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * All those INTC hookups (direct, plus several IRQ banks) can also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * serve as EDMA event triggers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static void gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct davinci_gpio_regs __iomem *g = irq2regs(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) writel_relaxed(mask, &g->clr_falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) writel_relaxed(mask, &g->clr_rising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void gpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct davinci_gpio_regs __iomem *g = irq2regs(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned status = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (status & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) writel_relaxed(mask, &g->set_falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (status & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writel_relaxed(mask, &g->set_rising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int gpio_irq_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static struct irq_chip gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .name = "GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .irq_enable = gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .irq_disable = gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .irq_set_type = gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .flags = IRQCHIP_SET_TYPE_MASKED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) u32 mask = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct davinci_gpio_controller *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct davinci_gpio_irq_data *irqdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bank_num = irqdata->bank_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) g = irqdata->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) d = irqdata->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* we only care about one bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if ((bank_num % 2) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mask <<= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* temporarily mask (level sensitive) parent IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) chained_irq_enter(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) irq_hw_number_t hw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* ack any irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) status = readl_relaxed(&g->intstat) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) writel_relaxed(status, &g->intstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* now demux them to the right lowlevel handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bit = __ffs(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) status &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Max number of gpios per controller is 144 so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * hw_irq will be in [0..143]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) hw_irq = (bank_num / 2) * 32 + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) irq_find_mapping(d->irq_domain, hw_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) chained_irq_exit(irq_desc_get_chip(desc), desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* now it may re-trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct davinci_gpio_controller *d = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (d->irq_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return irq_create_mapping(d->irq_domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct davinci_gpio_controller *d = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * NOTE: we assume for now that only irqs in the first gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (offset < d->gpio_unbanked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return d->irqs[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct davinci_gpio_controller *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 mask, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) g = (struct davinci_gpio_regs __iomem *)d->regs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < MAX_INT_PER_BANK; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (data->irq == d->irqs[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (i == MAX_INT_PER_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mask = __gpio_mask(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ? &g->set_falling : &g->clr_falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ? &g->set_rising : &g->clr_rising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct davinci_gpio_controller *chips =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) (struct davinci_gpio_controller *)d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) "davinci_gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) irq_set_irq_type(irq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) irq_set_chip_data(irq, (__force void *)g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct irq_domain_ops davinci_gpio_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .map = davinci_gpio_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static struct irq_chip_type gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return &gpio_unbanked.chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct irq_chip gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gpio_unbanked = *irq_get_chip(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return &gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static const struct of_device_id davinci_gpio_ids[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * NOTE: for suspend/resume, probably best to make a platform_device with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * suspend_late/resume_resume calls hooking into results of the set_wake()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * calls ... so if no gpios are wakeup events the clock can be disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * (dm6446) can be set appropriately for GPIOV33 pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int davinci_gpio_irq_setup(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned gpio, bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 binten = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct davinci_gpio_platform_data *pdata = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct davinci_gpio_regs __iomem *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct irq_domain *irq_domain = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct davinci_gpio_irq_data *irqdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) gpio_get_irq_chip_cb_t gpio_get_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * Use davinci_gpio_get_irq_chip by default to handle non DT cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) gpio_get_irq_chip = davinci_gpio_get_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) match = of_match_device(of_match_ptr(davinci_gpio_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ngpio = pdata->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) clk = devm_clk_get(dev, "gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = clk_prepare_enable(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!pdata->gpio_unbanked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(dev, "Couldn't allocate IRQ numbers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &davinci_gpio_irq_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_err(dev, "Couldn't register an IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * Arrange gpio_to_irq() support, handling either direct IRQs or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * banked IRQs. Having GPIOs in the first GPIO bank use direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * IRQs, while the others use banked IRQs, would need some setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * tweaks to recognize hardware which can do that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) chips->chip.to_irq = gpio_to_irq_banked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) chips->irq_domain = irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * controller only handling trigger modes. We currently assume no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (pdata->gpio_unbanked) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* pass "bank 0" GPIO IRQs to AINTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) chips->chip.to_irq = gpio_to_irq_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) chips->gpio_unbanked = pdata->gpio_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) binten = GENMASK(pdata->gpio_unbanked / 16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* AINTC handles mask/unmask; GPIO handles triggering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) irq = chips->irqs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) irq_chip = gpio_get_irq_chip(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) irq_chip->name = "GPIO-AINTC";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) irq_chip->irq_set_type = gpio_irq_type_unbanked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* default trigger: both edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) g = chips->regs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) writel_relaxed(~0, &g->set_falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) writel_relaxed(~0, &g->set_rising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* set the direct IRQs up to use that irqchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) irq_set_chip(chips->irqs[gpio], irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) irq_set_handler_data(chips->irqs[gpio], chips);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) irq_set_status_flags(chips->irqs[gpio],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) IRQ_TYPE_EDGE_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * then chain through our own handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* disabled by default, enabled only as needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * There are register sets for 32 GPIOs. 2 banks of 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * GPIOs are covered by each set of registers hence divide by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) g = chips->regs[bank / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) writel_relaxed(~0, &g->clr_falling);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writel_relaxed(~0, &g->clr_rising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Each chip handles 32 gpios, and each irq bank consists of 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * gpio irqs. Pass the irq bank's corresponding controller to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * the chained irq handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) irqdata = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) sizeof(struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) davinci_gpio_irq_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!irqdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk_disable_unprepare(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) irqdata->regs = g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) irqdata->bank_num = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) irqdata->chip = chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) irq_set_chained_handler_and_data(chips->irqs[bank],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) gpio_irq_handler, irqdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) binten |= BIT(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * BINTEN -- per-bank interrupt enable. genirq would also let these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * bits be set/cleared dynamically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) writel_relaxed(binten, gpio_base + BINTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const struct of_device_id davinci_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static struct platform_driver davinci_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .probe = davinci_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "davinci_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .of_match_table = of_match_ptr(davinci_gpio_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * GPIO driver registration needs to be done before machine_init functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static int __init davinci_gpio_drv_reg(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return platform_driver_register(&davinci_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) postcore_initcall(davinci_gpio_drv_reg);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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