^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO Driver for Dialog DA9052 PMICs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright(c) 2011 Dialog Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: David Dajun Chen <dchen@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/fs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/syscalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/da9052/da9052.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/da9052/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/da9052/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DA9052_INPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DA9052_OUTPUT_OPENDRAIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DA9052_OUTPUT_PUSHPULL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DA9052_SUPPLY_VDD_IO1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DA9052_DEBOUNCING_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DA9052_DEBOUNCING_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DA9052_OUTPUT_LOWLEVEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DA9052_ACTIVE_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DA9052_ACTIVE_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DA9052_GPIO_MAX_PORTS_PER_REGISTER 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DA9052_GPIO_SHIFT_COUNT(no) (no%8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DA9052_GPIO_NIBBLE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DA9052_IRQ_GPI0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DA9052_GPIO_ODD_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DA9052_GPIO_EVEN_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct da9052_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct da9052 *da9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct gpio_chip gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static unsigned char da9052_gpio_port_odd(unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return offset % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static int da9052_gpio_get(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct da9052_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int da9052_port_direction = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = da9052_reg_read(gpio->da9052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DA9052_GPIO_0_1_REG + (offset >> 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (da9052_gpio_port_odd(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) da9052_port_direction = ret & DA9052_GPIO_ODD_PORT_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) da9052_port_direction >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) da9052_port_direction = ret & DA9052_GPIO_EVEN_PORT_PIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) switch (da9052_port_direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) case DA9052_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (offset < DA9052_GPIO_MAX_PORTS_PER_REGISTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = da9052_reg_read(gpio->da9052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DA9052_STATUS_C_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ret = da9052_reg_read(gpio->da9052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DA9052_STATUS_D_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return !!(ret & (1 << DA9052_GPIO_SHIFT_COUNT(offset)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) case DA9052_OUTPUT_PUSHPULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (da9052_gpio_port_odd(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return !!(ret & DA9052_GPIO_ODD_PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return !!(ret & DA9052_GPIO_EVEN_PORT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct da9052_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (da9052_gpio_port_odd(offset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DA9052_GPIO_ODD_PORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) value << DA9052_GPIO_ODD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) dev_err(gpio->da9052->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "Failed to updated gpio odd reg,%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DA9052_GPIO_EVEN_PORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) value << DA9052_GPIO_EVEN_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(gpio->da9052->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) "Failed to updated gpio even reg,%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int da9052_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct da9052_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned char register_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Format: function - 2 bits type - 1 bit mode - 1 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) register_value = DA9052_INPUT | DA9052_ACTIVE_LOW << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DA9052_DEBOUNCING_ON << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (da9052_gpio_port_odd(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DA9052_GPIO_MASK_UPPER_NIBBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (register_value <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DA9052_GPIO_NIBBLE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DA9052_GPIO_MASK_LOWER_NIBBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) register_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int da9052_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct da9052_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned char register_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Format: Function - 2 bits Type - 1 bit Mode - 1 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) register_value = DA9052_OUTPUT_PUSHPULL | DA9052_SUPPLY_VDD_IO1 << 2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) value << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (da9052_gpio_port_odd(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DA9052_GPIO_MASK_UPPER_NIBBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (register_value <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) DA9052_GPIO_NIBBLE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DA9052_GPIO_0_1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) DA9052_GPIO_MASK_LOWER_NIBBLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) register_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int da9052_gpio_to_irq(struct gpio_chip *gc, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct da9052_gpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct da9052 *da9052 = gpio->da9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) irq = regmap_irq_get_virq(da9052->irq_data, DA9052_IRQ_GPI0 + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct gpio_chip reference_gp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .label = "da9052-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .get = da9052_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .set = da9052_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .direction_input = da9052_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .direction_output = da9052_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .to_irq = da9052_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .can_sleep = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .ngpio = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int da9052_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct da9052_gpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct da9052_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) gpio->da9052 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pdata = dev_get_platdata(gpio->da9052->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) gpio->gp = reference_gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (pdata && pdata->gpio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) gpio->gp.base = pdata->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = devm_gpiochip_add_data(&pdev->dev, &gpio->gp, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) platform_set_drvdata(pdev, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct platform_driver da9052_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .probe = da9052_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "da9052-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) module_platform_driver(da9052_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MODULE_DESCRIPTION("DA9052 GPIO Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_ALIAS("platform:da9052-gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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