Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AMD CS5535/CS5536 GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2006  Advanced Micro Devices, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2007-2009  Andres Salomon <dilinger@collabora.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/cs5535.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/msr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define DRV_NAME "cs5535-gpio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * Some GPIO pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  31-29,23 : reserved (always mask out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *  28       : Power Button
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *  26       : PME#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *  22-16    : LPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *  14,15    : SMBus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *  9,8      : UART1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *  7        : PCI INTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *  3,4      : UART2/DDC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *  2        : IDE_IRQ0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *  1        : AC_BEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *  0        : PCI INTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * If a mask was not specified, allow all except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * reserved and Power Button
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define GPIO_DEFAULT_MASK 0x0F7FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static ulong mask = GPIO_DEFAULT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) module_param_named(mask, mask, ulong, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) MODULE_PARM_DESC(mask, "GPIO channel mask.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * FIXME: convert this singleton driver to use the state container
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * design pattern, see Documentation/driver-api/driver-model/design-patterns.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static struct cs5535_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	resource_size_t base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) } cs5535_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * The CS5535/CS5536 GPIOs support a number of extra features not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * by the gpio_chip API, so these are exported.  For a full list of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * registers, see include/linux/cs5535.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static void errata_outl(struct cs5535_gpio_chip *chip, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	unsigned long addr = chip->base + 0x80 + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	 * According to the CS5536 errata (#36), after suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	 * a write to the high bank GPIO register will clear all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	 * non-selected bits; the recommended workaround is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	 * read-modify-write operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	 * Don't apply this errata to the edge status GPIOs, as writing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * to their lower bits will clear them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	if (reg != GPIO_POSITIVE_EDGE_STS && reg != GPIO_NEGATIVE_EDGE_STS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (val & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			val |= (inl(addr) & 0xffff); /* ignore the high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			val |= (inl(addr) ^ (val >> 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	outl(val, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static void __cs5535_gpio_set(struct cs5535_gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		/* low bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		outl(1 << offset, chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		/* high bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		errata_outl(chip, 1 << (offset - 16), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) void cs5535_gpio_set(unsigned offset, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	__cs5535_gpio_set(chip, offset, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) EXPORT_SYMBOL_GPL(cs5535_gpio_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void __cs5535_gpio_clear(struct cs5535_gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		/* low bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		outl(1 << (offset + 16), chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		/* high bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		errata_outl(chip, 1 << offset, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void cs5535_gpio_clear(unsigned offset, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	__cs5535_gpio_clear(chip, offset, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXPORT_SYMBOL_GPL(cs5535_gpio_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int cs5535_gpio_isset(unsigned offset, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* low bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		val = inl(chip->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/* high bank register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		val = inl(chip->base + 0x80 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		offset -= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return (val & (1 << offset)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXPORT_SYMBOL_GPL(cs5535_gpio_isset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int cs5535_gpio_set_irq(unsigned group, unsigned irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	uint32_t lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (group > 7 || irq > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	lo &= ~(0xF << (group * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	lo |= (irq & 0xF) << (group * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) EXPORT_SYMBOL_GPL(cs5535_gpio_set_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void cs5535_gpio_setup_event(unsigned offset, int pair, int pme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	struct cs5535_gpio_chip *chip = &cs5535_gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	uint32_t shift = (offset % 8) * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (offset >= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		offset = GPIO_MAP_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	else if (offset >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		offset = GPIO_MAP_Z;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	else if (offset >= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		offset = GPIO_MAP_Y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		offset = GPIO_MAP_X;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	val = inl(chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	/* Clear whatever was there before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	val &= ~(0xF << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	/* Set the new value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	val |= ((pair & 7) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* Set the PME bit if this is a PME event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (pme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		val |= (1 << (shift + 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	outl(val, chip->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) EXPORT_SYMBOL_GPL(cs5535_gpio_setup_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  * Generic gpio_chip API support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int chip_gpio_request(struct gpio_chip *c, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* check if this pin is available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if ((mask & (1 << offset)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		dev_info(&chip->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			"pin %u is not available (check mask)\n", offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* disable output aux 1 & 2 on this pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_AUX2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* disable input aux 1 on this pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	__cs5535_gpio_clear(chip, offset, GPIO_INPUT_AUX1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int chip_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return cs5535_gpio_isset(offset, GPIO_READ_BACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void chip_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		cs5535_gpio_set(offset, GPIO_OUTPUT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		cs5535_gpio_clear(offset, GPIO_OUTPUT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int chip_direction_input(struct gpio_chip *c, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int chip_direction_output(struct gpio_chip *c, unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct cs5535_gpio_chip *chip = gpiochip_get_data(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	spin_lock_irqsave(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	__cs5535_gpio_set(chip, offset, GPIO_INPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		__cs5535_gpio_set(chip, offset, GPIO_OUTPUT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		__cs5535_gpio_clear(chip, offset, GPIO_OUTPUT_VAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	spin_unlock_irqrestore(&chip->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const char * const cs5535_gpio_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	"GPIO0", "GPIO1", "GPIO2", "GPIO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	"GPIO4", "GPIO5", "GPIO6", "GPIO7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	"GPIO8", "GPIO9", "GPIO10", "GPIO11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	"GPIO12", "GPIO13", "GPIO14", "GPIO15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	"GPIO16", "GPIO17", "GPIO18", "GPIO19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	"GPIO20", "GPIO21", "GPIO22", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	"GPIO24", "GPIO25", "GPIO26", "GPIO27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	"GPIO28", NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct cs5535_gpio_chip cs5535_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.label = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.ngpio = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.names = cs5535_gpio_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.request = chip_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.get = chip_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.set = chip_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.direction_input = chip_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.direction_output = chip_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int cs5535_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ulong mask_orig = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/* There are two ways to get the GPIO base address; one is by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * fetching it from MSR_LBAR_GPIO, the other is by reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * PCI BAR info.  The latter method is easier (especially across
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 * different architectures), so we'll stick with that for now.  If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	 * it turns out to be unreliable in the face of crappy BIOSes, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	 * can always go back to using MSRs.. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		dev_err(&pdev->dev, "can't fetch device resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 				 pdev->name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		dev_err(&pdev->dev, "can't request region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* set up the driver-specific struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	cs5535_gpio_chip.base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	cs5535_gpio_chip.pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	spin_lock_init(&cs5535_gpio_chip.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	dev_info(&pdev->dev, "reserved resource region %pR\n", res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	/* mask out reserved pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	mask &= 0x1F7FFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	/* do not allow pin 28, Power Button, as there's special handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	 * in the PMC needed. (note 12, p. 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	mask &= ~(1 << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (mask_orig != mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		dev_info(&pdev->dev, "mask changed from 0x%08lX to 0x%08lX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				mask_orig, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	/* finally, register with the generic GPIO API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	err = devm_gpiochip_add_data(&pdev->dev, &cs5535_gpio_chip.chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 				     &cs5535_gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_driver cs5535_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		.name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.probe = cs5535_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) module_platform_driver(cs5535_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MODULE_DESCRIPTION("AMD CS5535/CS5536 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MODULE_ALIAS("platform:" DRV_NAME);