Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Intel Crystal Cove GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2012, 2014 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Yang, Bin <bin.yang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mfd/intel_soc_pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CRYSTALCOVE_GPIO_NUM	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CRYSTALCOVE_VGPIO_NUM	95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UPDATE_IRQ_TYPE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define UPDATE_IRQ_MASK		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define GPIO0IRQ		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define GPIO1IRQ		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MGPIO0IRQS0		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MGPIO1IRQS0		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MGPIO0IRQSX		0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MGPIO1IRQSX		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define GPIO0P0CTLO		0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define GPIO0P0CTLI		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define GPIO1P0CTLO		0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define GPIO1P0CTLI		0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define GPIOPANELCTL		0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CTLI_INTCNT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CTLI_INTCNT_NE		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CTLI_INTCNT_PE		(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CTLI_INTCNT_BE		(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CTLO_DIR_IN		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CTLO_DIR_OUT		(1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CTLO_DRV_CMOS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CTLO_DRV_OD		(1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CTLO_DRV_REN		(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CTLO_RVAL_2KDW		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CTLO_RVAL_2KUP		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CTLO_RVAL_50KDW		(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CTLO_RVAL_50KUP		(3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CTLO_INPUT_SET	(CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CTLO_OUTPUT_SET	(CTLO_DIR_OUT | CTLO_INPUT_SET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) enum ctrl_register {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	CTRL_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	CTRL_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * struct crystalcove_gpio - Crystal Cove GPIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * @buslock: for bus lock/sync and unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * @chip: the abstract gpio_chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * @regmap: the regmap from the parent device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * @update: pending IRQ setting update, to be written to the chip upon unlock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * @intcnt_value: the Interrupt Detect value to be written.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * @set_irq_mask: true if the IRQ mask needs to be set, false to clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct crystalcove_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct mutex buslock; /* irq_bus_lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int intcnt_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	bool set_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline int to_reg(int gpio, enum ctrl_register reg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	if (gpio >= CRYSTALCOVE_GPIO_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 * Virtual GPIO called from ACPI, for now we only support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		 * the panel ctl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		switch (gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		case 0x5e:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			return GPIOPANELCTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (reg_type == CTRL_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (gpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 			reg = GPIO0P0CTLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			reg = GPIO1P0CTLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (gpio < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			reg = GPIO0P0CTLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			reg = GPIO1P0CTLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return reg + gpio % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	int mask = BIT(gpio % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (cg->set_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	int reg = to_reg(gpio, CTRL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				    int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int ret, reg = to_reg(gpio, CTRL_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	ret = regmap_read(cg->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return val & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void crystalcove_gpio_set(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				 unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int reg = to_reg(gpio, CTRL_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		regmap_update_bits(cg->regmap, reg, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		regmap_update_bits(cg->regmap, reg, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int crystalcove_irq_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct crystalcove_gpio *cg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (data->hwirq >= CRYSTALCOVE_GPIO_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		cg->intcnt_value = CTLI_INTCNT_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		cg->intcnt_value = CTLI_INTCNT_BE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		cg->intcnt_value = CTLI_INTCNT_PE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		cg->intcnt_value = CTLI_INTCNT_NE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	cg->update |= UPDATE_IRQ_TYPE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void crystalcove_bus_lock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct crystalcove_gpio *cg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mutex_lock(&cg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static void crystalcove_bus_sync_unlock(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct crystalcove_gpio *cg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int gpio = data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (cg->update & UPDATE_IRQ_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		crystalcove_update_irq_ctrl(cg, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (cg->update & UPDATE_IRQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		crystalcove_update_irq_mask(cg, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	cg->update = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	mutex_unlock(&cg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static void crystalcove_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct crystalcove_gpio *cg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		cg->set_irq_mask = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		cg->update |= UPDATE_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void crystalcove_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	struct crystalcove_gpio *cg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		gpiochip_get_data(irq_data_get_irq_chip_data(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (data->hwirq < CRYSTALCOVE_GPIO_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		cg->set_irq_mask = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		cg->update |= UPDATE_IRQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct irq_chip crystalcove_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.name			= "Crystal Cove",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.irq_mask		= crystalcove_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.irq_unmask		= crystalcove_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.irq_set_type		= crystalcove_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.irq_bus_lock		= crystalcove_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.irq_bus_sync_unlock	= crystalcove_bus_sync_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.flags			= IRQCHIP_SKIP_SET_WAKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct crystalcove_gpio *cg = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	unsigned int p0, p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	regmap_write(cg->regmap, GPIO0IRQ, p0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	regmap_write(cg->regmap, GPIO1IRQ, p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	pending = p0 | p1 << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		virq = irq_find_mapping(cg->chip.irq.domain, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		handle_nested_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void crystalcove_gpio_dbg_show(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				      struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct crystalcove_gpio *cg = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int gpio, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	unsigned int ctlo, ctli, mirqs0, mirqsx, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			    &mirqs0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			    &mirqsx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			    &irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		offset = gpio % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			   gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			   ctli & 0x1 ? "hi" : "lo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			   ctli & CTLI_INTCNT_NE ? "fall" : "    ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			   ctli & CTLI_INTCNT_PE ? "rise" : "    ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			   ctlo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			   mirqs0 & BIT(offset) ? "s0 mask  " : "s0 unmask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			   mirqsx & BIT(offset) ? "sx mask  " : "sx unmask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			   irq & BIT(offset) ? "pending" : "       ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int crystalcove_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	struct crystalcove_gpio *cg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct device *dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (!cg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	platform_set_drvdata(pdev, cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	mutex_init(&cg->buslock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	cg->chip.label = KBUILD_MODNAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	cg->chip.direction_input = crystalcove_gpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	cg->chip.direction_output = crystalcove_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	cg->chip.get = crystalcove_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	cg->chip.set = crystalcove_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	cg->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	cg->chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	cg->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	cg->regmap = pmic->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	girq = &cg->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	girq->chip = &crystalcove_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	/* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	retval = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 					   crystalcove_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 					   IRQF_ONESHOT, KBUILD_MODNAME, cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		dev_warn(&pdev->dev, "request irq failed: %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (retval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static struct platform_driver crystalcove_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.probe = crystalcove_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		.name = "crystal_cove_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) module_platform_driver(crystalcove_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_LICENSE("GPL v2");