^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Synopsys CREG (Control REGisters) GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (C) 2018 Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MAX_GPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct creg_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u8 ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) u8 shift[MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u8 on[MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 off[MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u8 bit_per_gpio[MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct creg_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) const struct creg_layout *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void creg_gpio_set(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct creg_gpio *hcg = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct creg_layout *layout = hcg->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 reg, reg_shift, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) value = val ? hcg->layout->on[offset] : hcg->layout->off[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) reg_shift = layout->shift[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (i = 0; i < offset; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) reg_shift += layout->bit_per_gpio[i] + layout->shift[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spin_lock_irqsave(&hcg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg = readl(hcg->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg &= ~(GENMASK(layout->bit_per_gpio[i] - 1, 0) << reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg |= (value << reg_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) writel(reg, hcg->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) spin_unlock_irqrestore(&hcg->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int creg_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) creg_gpio_set(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int creg_gpio_validate_pg(struct device *dev, struct creg_gpio *hcg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const struct creg_layout *layout = hcg->layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (layout->bit_per_gpio[i] < 1 || layout->bit_per_gpio[i] > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Check that on value fits its placeholder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (GENMASK(31, layout->bit_per_gpio[i]) & layout->on[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Check that off value fits its placeholder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (GENMASK(31, layout->bit_per_gpio[i]) & layout->off[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (layout->on[i] == layout->off[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int creg_gpio_validate(struct device *dev, struct creg_gpio *hcg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 reg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (hcg->layout->ngpio < 1 || hcg->layout->ngpio > MAX_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (ngpios < 1 || ngpios > hcg->layout->ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev_err(dev, "ngpios must be in [1:%u]\n", hcg->layout->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) for (i = 0; i < hcg->layout->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (creg_gpio_validate_pg(dev, hcg, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg_len += hcg->layout->shift[i] + hcg->layout->bit_per_gpio[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Check that we fit in 32 bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (reg_len > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct creg_layout hsdk_cs_ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .ngpio = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .shift = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .off = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .on = { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .bit_per_gpio = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct creg_layout axs10x_flsh_cs_ctl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ngpio = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .shift = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .off = { 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .on = { 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .bit_per_gpio = { 2 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct of_device_id creg_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .compatible = "snps,creg-gpio-axs10x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .data = &axs10x_flsh_cs_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .compatible = "snps,creg-gpio-hsdk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .data = &hsdk_cs_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }, { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int creg_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct creg_gpio *hcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) hcg = devm_kzalloc(dev, sizeof(struct creg_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!hcg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) hcg->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (IS_ERR(hcg->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return PTR_ERR(hcg->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) match = of_match_node(creg_gpio_ids, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hcg->layout = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (!hcg->layout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = of_property_read_u32(dev->of_node, "ngpios", &ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = creg_gpio_validate(dev, hcg, ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) spin_lock_init(&hcg->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) hcg->gc.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) hcg->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) hcg->gc.ngpio = ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) hcg->gc.set = creg_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) hcg->gc.direction_output = creg_gpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hcg->gc.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = devm_gpiochip_add_data(dev, &hcg->gc, hcg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_info(dev, "GPIO controller with %d gpios probed\n", ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct platform_driver creg_gpio_snps_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .name = "snps-creg-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .of_match_table = creg_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .probe = creg_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) builtin_platform_driver(creg_gpio_snps_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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