^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 Cadence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jan Kotas <jank@cadence.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Boris Brezillon <boris.brezillon@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CDNS_GPIO_BYPASS_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CDNS_GPIO_DIRECTION_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CDNS_GPIO_OUTPUT_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CDNS_GPIO_OUTPUT_VALUE 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CDNS_GPIO_INPUT_VALUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CDNS_GPIO_IRQ_MASK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CDNS_GPIO_IRQ_EN 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CDNS_GPIO_IRQ_DIS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CDNS_GPIO_IRQ_STATUS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CDNS_GPIO_IRQ_TYPE 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CDNS_GPIO_IRQ_VALUE 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CDNS_GPIO_IRQ_ANY_EDGE 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct cdns_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 bypass_orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int cdns_gpio_request(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) spin_lock_irqsave(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) cgpio->regs + CDNS_GPIO_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) spin_unlock_irqrestore(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void cdns_gpio_free(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) spin_lock_irqsave(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (BIT(offset) & cgpio->bypass_orig),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cgpio->regs + CDNS_GPIO_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) spin_unlock_irqrestore(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void cdns_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void cdns_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) iowrite32(BIT(d->hwirq), cgpio->regs + CDNS_GPIO_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int cdns_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 int_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 int_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 mask = BIT(d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_lock_irqsave(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int_value = ioread32(cgpio->regs + CDNS_GPIO_IRQ_VALUE) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int_type = ioread32(cgpio->regs + CDNS_GPIO_IRQ_TYPE) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * The GPIO controller doesn't have an ACK register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * All interrupt statuses are cleared on a status register read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * Don't support edge interrupts for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (type == IRQ_TYPE_LEVEL_HIGH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int_type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int_value |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } else if (type == IRQ_TYPE_LEVEL_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int_type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto err_irq_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) iowrite32(int_value, cgpio->regs + CDNS_GPIO_IRQ_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) iowrite32(int_type, cgpio->regs + CDNS_GPIO_IRQ_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err_irq_type:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spin_unlock_irqrestore(&chip->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void cdns_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct gpio_chip *chip = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct cdns_gpio_chip *cgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) status = ioread32(cgpio->regs + CDNS_GPIO_IRQ_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ~ioread32(cgpio->regs + CDNS_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for_each_set_bit(hwirq, &status, chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) generic_handle_irq(irq_find_mapping(chip->irq.domain, hwirq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct irq_chip cdns_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "cdns-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .irq_mask = cdns_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .irq_unmask = cdns_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .irq_set_type = cdns_gpio_irq_set_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static int cdns_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct cdns_gpio_chip *cgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 dir_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 num_gpios = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) cgpio = devm_kzalloc(&pdev->dev, sizeof(*cgpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (!cgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) cgpio->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (IS_ERR(cgpio->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return PTR_ERR(cgpio->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) of_property_read_u32(pdev->dev.of_node, "ngpios", &num_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (num_gpios > 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dev_err(&pdev->dev, "ngpios must be less or equal 32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Set all pins as inputs by default, otherwise:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * gpiochip_lock_as_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * tried to flag a GPIO set as output for IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Generic GPIO driver stores the direction value internally,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * so it needs to be changed before bgpio_init() is called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dir_prev = ioread32(cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) iowrite32(GENMASK(num_gpios - 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = bgpio_init(&cgpio->gc, &pdev->dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) cgpio->regs + CDNS_GPIO_INPUT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) cgpio->regs + CDNS_GPIO_OUTPUT_VALUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) cgpio->regs + CDNS_GPIO_DIRECTION_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BGPIOF_READ_OUTPUT_REG_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(&pdev->dev, "Failed to register generic gpio, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto err_revert_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) cgpio->gc.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) cgpio->gc.ngpio = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) cgpio->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) cgpio->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) cgpio->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cgpio->gc.request = cdns_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) cgpio->gc.free = cdns_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cgpio->pclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (IS_ERR(cgpio->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = PTR_ERR(cgpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "Failed to retrieve peripheral clock, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto err_revert_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = clk_prepare_enable(cgpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "Failed to enable the peripheral clock, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto err_revert_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Optional irq_chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) girq = &cgpio->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) girq->chip = &cdns_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) girq->parent_handler = cdns_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (!girq->parents) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = devm_gpiochip_add_data(&pdev->dev, &cgpio->gc, cgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto err_disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cgpio->bypass_orig = ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Enable gpio outputs, ignored for input direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) iowrite32(GENMASK(num_gpios - 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) cgpio->regs + CDNS_GPIO_OUTPUT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) iowrite32(0, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) platform_set_drvdata(pdev, cgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) err_disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) clk_disable_unprepare(cgpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) err_revert_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) iowrite32(dir_prev, cgpio->regs + CDNS_GPIO_DIRECTION_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int cdns_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct cdns_gpio_chip *cgpio = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) iowrite32(cgpio->bypass_orig, cgpio->regs + CDNS_GPIO_BYPASS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) clk_disable_unprepare(cgpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct of_device_id cdns_of_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { .compatible = "cdns,gpio-r1p02" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MODULE_DEVICE_TABLE(of, cdns_of_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct platform_driver cdns_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .name = "cdns-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .of_match_table = cdns_of_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .probe = cdns_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .remove = cdns_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) module_platform_driver(cdns_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MODULE_AUTHOR("Jan Kotas <jank@cadence.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MODULE_DESCRIPTION("Cadence GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_ALIAS("platform:cdns-gpio");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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