^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2015-2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) enum gio_reg_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) GIO_REG_ODEN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) GIO_REG_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) GIO_REG_IODIR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) GIO_REG_EC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) GIO_REG_EI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) GIO_REG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) GIO_REG_LEVEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) GIO_REG_STAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) NUMBER_OF_GIO_REGISTERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GIO_BANK_SIZE (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct brcmstb_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct brcmstb_gpio_priv *parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 wake_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct brcmstb_gpio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct list_head bank_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int parent_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int parent_wake_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX_GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPIO_BANK(gpio) ((gpio) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline struct brcmstb_gpio_priv *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *reg_base = bank->parent_priv->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) status = __brcmstb_gpio_get_active_irqs(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int hwirq, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct gpio_chip *gc = &bank->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct brcmstb_gpio_priv *priv = bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) spin_lock_irqsave(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) imask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) imask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spin_unlock_irqrestore(&gc->bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* gc_offset is relative to this gpio_chip; want real offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int hwirq = offset + (gc->base - priv->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (hwirq >= priv->num_gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return irq_create_mapping(priv->irq_domain, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* -------------------- IRQ chip functions -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void brcmstb_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) brcmstb_gpio_set_imask(bank, d->hwirq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static void brcmstb_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) brcmstb_gpio_set_imask(bank, d->hwirq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static void brcmstb_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct brcmstb_gpio_priv *priv = bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct brcmstb_gpio_priv *priv = bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 edge_insensitive, iedge_insensitive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 edge_config, iedge_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 level, ilevel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) level = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) edge_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) edge_insensitive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) level = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) edge_config = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) edge_insensitive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) edge_config = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) edge_insensitive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) edge_config = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) edge_insensitive = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) level = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) edge_config = 0; /* don't care, but want known value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) edge_insensitive = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) iedge_config = bank->gc.read_reg(priv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) GIO_EC(bank->id)) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) iedge_insensitive = bank->gc.read_reg(priv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) GIO_EI(bank->id)) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ilevel = bank->gc.read_reg(priv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) GIO_LEVEL(bank->id)) & ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) iedge_config | edge_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) iedge_insensitive | edge_insensitive);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ilevel | level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ret = enable_irq_wake(priv->parent_wake_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ret = disable_irq_wake(priv->parent_wake_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enable ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct brcmstb_gpio_priv *priv = bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Do not do anything specific for now, suspend/resume callbacks will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * configure the interrupt mask appropriately
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bank->wake_active |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bank->wake_active &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return brcmstb_gpio_priv_set_wake(priv, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct brcmstb_gpio_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!priv || irq != priv->parent_wake_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Nothing to do */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct brcmstb_gpio_priv *priv = bank->parent_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct irq_domain *domain = priv->irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int hwbase = bank->gc.base - priv->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) while ((status = brcmstb_gpio_get_active_irqs(bank))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int irq, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for_each_set_bit(offset, &status, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (offset >= bank->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_warn(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bank->id, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) irq = irq_linear_revmap(domain, hwbase + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* Each UPG GIO block has one IRQ for all banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Interrupts weren't properly cleared during probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BUG_ON(!priv || !chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) list_for_each_entry(bank, &priv->bank_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) brcmstb_gpio_irq_bank_handler(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* banks are in descending order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) list_for_each_entry_reverse(bank, &priv->bank_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) i += bank->gc.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (hwirq < i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * This lock class tells lockdep that GPIO irqs are in a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * category than their parents, so it won't report false recursion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static struct lock_class_key brcmstb_gpio_irq_lock_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct lock_class_key brcmstb_gpio_irq_request_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct brcmstb_gpio_priv *priv = d->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct brcmstb_gpio_bank *bank =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) brcmstb_gpio_hwirq_to_bank(priv, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct platform_device *pdev = priv->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) irq, (int)hwirq, bank->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = irq_set_chip_data(irq, &bank->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &brcmstb_gpio_irq_request_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) irq_set_chip_and_handler(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .map = brcmstb_gpio_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .unmap = brcmstb_gpio_irq_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Make sure that the number of banks matches up between properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int brcmstb_gpio_sanity_check_banks(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct device_node *np, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int num_banks =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (res_num_banks != num_banks) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) res_num_banks, num_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static int brcmstb_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int offset, ret = 0, virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (priv->parent_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Remove all IRQ mappings and delete the domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (priv->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) for (offset = 0; offset < priv->num_gpios; offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) virq = irq_find_mapping(priv->irq_domain, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) irq_dispose_mapping(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) irq_domain_remove(priv->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * You can lose return values below, but we report all errors, and it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * more important to actually perform all of the steps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) list_for_each_entry(bank, &priv->bank_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gpiochip_remove(&bank->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) const struct of_phandle_args *gpiospec, u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (gc->of_gpio_n_cells != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (offset >= gc->ngpio || offset < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (unlikely(offset >= bank->width)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_warn_ratelimited(&priv->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "Received request for invalid GPIO offset %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) gpiospec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *flags = gpiospec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* priv->parent_irq and priv->num_gpios must be set before calling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct brcmstb_gpio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) priv->irq_domain =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) irq_domain_add_linear(np, priv->num_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &brcmstb_gpio_irq_domain_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!priv->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_err(dev, "Couldn't allocate IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (of_property_read_bool(np, "wakeup-source")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) priv->parent_wake_irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (priv->parent_wake_irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) priv->parent_wake_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Set wakeup capability so we can process boot-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * "wakeups" (e.g., from S5 cold boot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) device_set_wakeup_capable(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) device_wakeup_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) err = devm_request_irq(dev, priv->parent_wake_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) brcmstb_gpio_wake_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "brcmstb-gpio-wake", priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev_err(dev, "Couldn't request wake IRQ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) goto out_free_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) priv->irq_chip.name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (priv->parent_wake_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) irq_set_chained_handler_and_data(priv->parent_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) brcmstb_gpio_irq_handler, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) out_free_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) irq_domain_remove(priv->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct gpio_chip *gc = &bank->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (i = 0; i < GIO_REG_STAT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bank->saved_regs[i] = gc->read_reg(priv->reg_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GIO_BANK_OFF(bank->id, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void brcmstb_gpio_quiesce(struct device *dev, bool save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* disable non-wake interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (priv->parent_irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) disable_irq(priv->parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) list_for_each_entry(bank, &priv->bank_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) gc = &bank->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) brcmstb_gpio_bank_save(priv, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Unmask GPIOs which have been flagged as wake-up sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (priv->parent_wake_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) imask = bank->wake_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) imask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static void brcmstb_gpio_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Enable GPIO for S5 cold boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) brcmstb_gpio_quiesce(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct gpio_chip *gc = &bank->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (i = 0; i < GIO_REG_STAT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bank->saved_regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int brcmstb_gpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) brcmstb_gpio_quiesce(dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int brcmstb_gpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bool need_wakeup_event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) list_for_each_entry(bank, &priv->bank_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) brcmstb_gpio_bank_restore(priv, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (priv->parent_wake_irq && need_wakeup_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pm_wakeup_event(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* enable non-wake interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (priv->parent_irq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) enable_irq(priv->parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define brcmstb_gpio_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define brcmstb_gpio_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .suspend_noirq = brcmstb_gpio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .resume_noirq = brcmstb_gpio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void brcmstb_gpio_set_names(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct brcmstb_gpio_bank *bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) const char **names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int nstrings, base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) base = bank->id * MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) nstrings = of_property_count_strings(np, "gpio-line-names");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (nstrings <= base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Line names not present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) names = devm_kcalloc(dev, MAX_GPIO_PER_BANK, sizeof(*names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Make sure to not index beyond the end of the number of descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * of the GPIO device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < bank->width; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = of_property_read_string_index(np, "gpio-line-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) base + i, &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (ret != -ENODATA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dev_err(dev, "unable to name line %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) base + i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (*name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) names[i] = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bank->gc.names = names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static int brcmstb_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct brcmstb_gpio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const __be32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 bank_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int num_banks = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) bool need_wakeup_event = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) INIT_LIST_HEAD(&priv->bank_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) reg_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (IS_ERR(reg_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return PTR_ERR(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) priv->gpio_base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) priv->reg_base = reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) priv->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (of_property_read_bool(np, "interrupt-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) priv->parent_irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (priv->parent_irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) priv->parent_irq = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (brcmstb_gpio_sanity_check_banks(dev, np, res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * MIPS endianness is configured by boot strap, which also reverses all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * bus endianness (i.e., big-endian CPU + big endian bus ==> native
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * endian I/O).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * Other architectures (e.g., ARM) either do not support big endian, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * else leave I/O in little endian mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) bank_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct brcmstb_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * If bank_width is 0, then there is an empty bank in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * register block. Special handling for this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (bank_width == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) num_banks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) num_banks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) gpio_base += MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) bank->parent_priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) bank->id = num_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) dev_err(dev, "Invalid bank width %d\n", bank_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bank->width = bank_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * Regs are 4 bytes wide, have data reg, no set/clear regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * and direction bits have 0 = output and 1 = input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) gc = &bank->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) err = bgpio_init(gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) reg_base + GIO_DATA(bank->id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) NULL, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) reg_base + GIO_IODIR(bank->id), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dev_err(dev, "bgpio_init() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) gc->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!gc->label) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) gc->base = gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) gc->of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) gc->of_xlate = brcmstb_gpio_of_xlate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* not all ngpio lines are valid, will use bank width later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) gc->ngpio = MAX_GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (priv->parent_irq > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) gc->to_irq = brcmstb_gpio_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * Mask all interrupts by default, since wakeup interrupts may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * be retained from S5 cold boot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) brcmstb_gpio_set_names(dev, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) err = gpiochip_add_data(gc, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(dev, "Could not add gpiochip for bank %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) bank->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) gpio_base += gc->ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) gc->base, gc->ngpio, bank->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Everything looks good, so add bank to list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) list_add(&bank->node, &priv->bank_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) num_banks++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) priv->num_gpios = gpio_base - priv->gpio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (priv->parent_irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) err = brcmstb_gpio_irq_setup(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (priv->parent_wake_irq && need_wakeup_event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) pm_wakeup_event(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) (void) brcmstb_gpio_remove(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const struct of_device_id brcmstb_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { .compatible = "brcm,brcmstb-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct platform_driver brcmstb_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .name = "brcmstb-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .of_match_table = brcmstb_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .pm = &brcmstb_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .probe = brcmstb_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .remove = brcmstb_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .shutdown = brcmstb_gpio_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) module_platform_driver(brcmstb_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MODULE_AUTHOR("Gregory Fong");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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