^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Broadcom Kona GPIO Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012-2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BCM_GPIO_PASSWD 0x00a5a501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GPIO_PER_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GPIO_MAX_BANK_NUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GPIO_BANK(gpio) ((gpio) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* There is a GPIO control register for each GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPIO_CONTROL(gpio) (0x00000100 + ((gpio) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* The remaining registers are per GPIO bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_GPPWR_OFFSET 0x00000520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_GPCTR0_DBR_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_GPCTR0_DBR_MASK 0x000001e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPIO_GPCTR0_ITR_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPIO_GPCTR0_ITR_MASK 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPIO_GPCTR0_IOTR_MASK 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LOCK_CODE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define UNLOCK_CODE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct bcm_kona_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int num_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct bcm_kona_gpio_bank *banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct bcm_kona_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Used in the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int bank_id, u32 lockcode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val |= BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val &= ~BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void __iomem *reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 val, reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* this function only applies to output pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) val = readl(reg_base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) writel(val, reg_base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 val, reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg_offset = GPIO_IN_STATUS(bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg_offset = GPIO_OUT_STATUS(bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* read the GPIO bank status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = readl(reg_base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* return the specified bit status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return !!(val & BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = readl(reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) val &= ~GPIO_GPCTR0_IOTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(val, reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 val, reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) val = readl(reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val &= ~GPIO_GPCTR0_IOTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) writel(val, reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val = readl(reg_base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) writel(val, reg_base + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (gpio >= kona_gpio->gpio_chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return irq_create_mapping(kona_gpio->irq_domain, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned debounce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 val, res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) kona_gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* debounce must be 1-128ms (or 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(chip->parent, "Debounce value %u not in range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* calculate debounce bit value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (debounce != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Convert to ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) debounce /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* find the MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) res = fls(debounce) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Check if MSB-1 is set (round up or down) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (res > 0 && (debounce & BIT(res - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) res++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* spin lock for read-modify-write of the GPIO register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = readl(reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val &= ~GPIO_GPCTR0_DBR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (debounce == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* disable debounce */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) val |= GPIO_GPCTR0_DB_ENABLE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (res << GPIO_GPCTR0_DBR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) writel(val, reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned long config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 debounce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) debounce = pinconf_to_config_argument(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const struct gpio_chip template_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .label = "bcm-kona-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .request = bcm_kona_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .free = bcm_kona_gpio_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .get_direction = bcm_kona_gpio_get_dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .direction_input = bcm_kona_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .get = bcm_kona_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .direction_output = bcm_kona_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .set = bcm_kona_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .set_config = bcm_kona_gpio_set_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .to_irq = bcm_kona_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .base = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void bcm_kona_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) val = readl(reg_base + GPIO_INT_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writel(val, reg_base + GPIO_INT_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void bcm_kona_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = readl(reg_base + GPIO_INT_MASK(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) writel(val, reg_base + GPIO_INT_MASK(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int bank_id = GPIO_BANK(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int bit = GPIO_BIT(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned gpio = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 lvl_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* BCM GPIO doesn't support level triggering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(kona_gpio->gpio_chip.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Invalid BCM GPIO irq type 0x%x\n", type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) raw_spin_lock_irqsave(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) val = readl(reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val &= ~GPIO_GPCTR0_ITR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel(val, reg_base + GPIO_CONTROL(gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int bit, bank_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned long sta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * For bank interrupts, we can't use chip_data to store the kona_gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * pointer, since GIC needs it for its own purposes. Therefore, we get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * our pointer from the bank structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg_base = bank->kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) bank_id = bank->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) for_each_set_bit(bit, &sta, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int hwirq = GPIO_PER_BANK * bank_id + bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int child_irq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) irq_find_mapping(bank->kona_gpio->irq_domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Clear interrupt before handler is called so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * miss any interrupt occurred during executing them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Invoke interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) generic_handle_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void bcm_kona_gpio_irq_relres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct irq_chip bcm_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "bcm-kona-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .irq_ack = bcm_kona_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .irq_mask = bcm_kona_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .irq_unmask = bcm_kona_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .irq_set_type = bcm_kona_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .irq_request_resources = bcm_kona_gpio_irq_reqres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .irq_release_resources = bcm_kona_gpio_irq_relres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct of_device_id const bcm_kona_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { .compatible = "brcm,kona-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * This lock class tells lockdep that GPIO irqs are in a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * category than their parents, so it won't report false recursion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static struct lock_class_key gpio_lock_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static struct lock_class_key gpio_request_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) irq_hw_number_t hwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = irq_set_chip_data(irq, d->host_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) irq_set_noprobe(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) irq_set_chip_and_handler(irq, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) irq_set_chip_data(irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct irq_domain_ops bcm_kona_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .map = bcm_kona_gpio_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .unmap = bcm_kona_gpio_irq_unmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) reg_base = kona_gpio->reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* disable interrupts and clear status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) for (i = 0; i < kona_gpio->num_bank; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Unlock the entire bank first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Now re-lock the bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int bcm_kona_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct bcm_kona_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct bcm_kona_gpio *kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) match = of_match_device(bcm_kona_gpio_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev_err(dev, "Failed to find gpio controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!kona_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) kona_gpio->gpio_chip = template_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) chip = &kona_gpio->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ret = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_err(dev, "Couldn't determine # GPIO banks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) kona_gpio->num_bank = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GPIO_MAX_BANK_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) kona_gpio->banks = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) kona_gpio->num_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) sizeof(*kona_gpio->banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!kona_gpio->banks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) kona_gpio->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) platform_set_drvdata(pdev, kona_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) chip->of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) chip->ngpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &bcm_kona_irq_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) kona_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!kona_gpio->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(dev, "Couldn't allocate IRQ domain\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (IS_ERR(kona_gpio->reg_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = PTR_ERR(kona_gpio->reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) goto err_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) for (i = 0; i < kona_gpio->num_bank; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) bank = &kona_gpio->banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) bank->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) bank->irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bank->kona_gpio = kona_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (bank->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(dev, "Couldn't get IRQ for bank %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) goto err_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_info(&pdev->dev, "Setting up Kona GPIO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bcm_kona_gpio_reset(kona_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) goto err_irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) for (i = 0; i < kona_gpio->num_bank; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bank = &kona_gpio->banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) irq_set_chained_handler_and_data(bank->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bcm_kona_gpio_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) raw_spin_lock_init(&kona_gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) err_irq_domain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) irq_domain_remove(kona_gpio->irq_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static struct platform_driver bcm_kona_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .name = "bcm-kona-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .of_match_table = bcm_kona_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .probe = bcm_kona_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) builtin_platform_driver(bcm_kona_gpio_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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