Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Atheros AR71XX/AR724X/AR913X GPIO API support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2015 Alban Bedel <albeu@free.fr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_data/gpio-ath79.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AR71XX_GPIO_REG_OE		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AR71XX_GPIO_REG_IN		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AR71XX_GPIO_REG_SET		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define AR71XX_GPIO_REG_CLEAR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AR71XX_GPIO_REG_INT_ENABLE	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define AR71XX_GPIO_REG_INT_TYPE	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AR71XX_GPIO_REG_INT_POLARITY	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AR71XX_GPIO_REG_INT_PENDING	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define AR71XX_GPIO_REG_INT_MASK	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct ath79_gpio_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned long both_edges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return container_of(gc, struct ath79_gpio_ctrl, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return readl(ctrl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			unsigned reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	writel(val, ctrl->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static bool ath79_gpio_update_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 old_val, new_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	old_val = ath79_gpio_read(ctrl, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	new_val = (old_val & ~mask) | (bits & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	if (new_val != old_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		ath79_gpio_write(ctrl, reg, new_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	return new_val != old_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void ath79_gpio_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static void ath79_gpio_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static void ath79_gpio_irq_enable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	u32 mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void ath79_gpio_irq_disable(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u32 mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int ath79_gpio_irq_set_type(struct irq_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	u32 type = 0, polarity = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bool disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	switch (flow_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		polarity |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		type |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	if (flow_type == IRQ_TYPE_EDGE_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		ctrl->both_edges |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		ctrl->both_edges &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* As the IRQ configuration can't be loaded atomically we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	 * have to disable the interrupt while the configuration state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	 * is invalid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	disabled = ath79_gpio_update_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ath79_gpio_update_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	ath79_gpio_update_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		ath79_gpio_update_bits(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static struct irq_chip ath79_gpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.name = "gpio-ath79",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.irq_enable = ath79_gpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.irq_disable = ath79_gpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.irq_mask = ath79_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.irq_unmask = ath79_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.irq_set_type = ath79_gpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void ath79_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct ath79_gpio_ctrl *ctrl =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		container_of(gc, struct ath79_gpio_ctrl, gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	unsigned long flags, pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 both_edges, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	raw_spin_lock_irqsave(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* Update the polarity of the both edges irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	both_edges = ctrl->both_edges & pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (both_edges) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 				both_edges, ~state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	raw_spin_unlock_irqrestore(&ctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		for_each_set_bit(irq, &pending, gc->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				irq_linear_revmap(gc->irq.domain, irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct of_device_id ath79_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ .compatible = "qca,ar7100-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ .compatible = "qca,ar9340-gpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MODULE_DEVICE_TABLE(of, ath79_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int ath79_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct ath79_gpio_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	u32 ath79_gpio_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	bool oe_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	platform_set_drvdata(pdev, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		err = of_property_read_u32(np, "ngpios", &ath79_gpio_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			dev_err(dev, "ngpios property is not valid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	} else if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		ath79_gpio_count = pdata->ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		oe_inverted = pdata->oe_inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		dev_err(dev, "No DT node or platform data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (ath79_gpio_count >= 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		dev_err(dev, "ngpios must be less than 32\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	ctrl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (IS_ERR(ctrl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return PTR_ERR(ctrl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	raw_spin_lock_init(&ctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	err = bgpio_init(&ctrl->gc, dev, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			ctrl->base + AR71XX_GPIO_REG_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			ctrl->base + AR71XX_GPIO_REG_SET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			ctrl->base + AR71XX_GPIO_REG_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		dev_err(dev, "bgpio_init failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	/* Use base 0 to stay compatible with legacy platforms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	ctrl->gc.base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	/* Optional interrupt setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!np || of_property_read_bool(np, "interrupt-controller")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		girq = &ctrl->gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		girq->chip = &ath79_gpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		girq->parent_handler = ath79_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 					     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		girq->parents[0] = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	err = devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			"cannot add AR71xx GPIO chip, error=%d", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static struct platform_driver ath79_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.name = "ath79-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.of_match_table	= ath79_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.probe = ath79_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) module_platform_driver(ath79_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_LICENSE("GPL v2");