Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2019 American Megatrends International LLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Karthikeyan Mani <karthikeyanm@amiindia.co.in>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/hashtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * slots within the clocked serial GPIO data). Since each HW GPIO is both an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MAX_NR_HW_SGPIO			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SGPIO_OUTPUT_OFFSET		MAX_NR_HW_SGPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ASPEED_SGPIO_CTRL		0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ASPEED_SGPIO_PINS_MASK		GENMASK(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define ASPEED_SGPIO_CLK_DIV_MASK	GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ASPEED_SGPIO_ENABLE		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct aspeed_sgpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int n_sgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct aspeed_sgpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	uint16_t    val_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	uint16_t    rdata_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	uint16_t    irq_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	const char  names[4][3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * Note: The "value" register returns the input value when the GPIO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *	 configured as an input.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *	 The "rdata" register returns the output value when the GPIO is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *	 configured as an output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.val_regs = 0x0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.rdata_reg = 0x0070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.irq_regs = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.names = { "A", "B", "C", "D" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.val_regs = 0x001C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.rdata_reg = 0x0074,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.irq_regs = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.names = { "E", "F", "G", "H" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.val_regs = 0x0038,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.rdata_reg = 0x0078,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.irq_regs = 0x003C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.names = { "I", "J" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) enum aspeed_sgpio_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	reg_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	reg_rdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	reg_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	reg_irq_type0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	reg_irq_type1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	reg_irq_type2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	reg_irq_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define GPIO_VAL_VALUE      0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define GPIO_IRQ_ENABLE     0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define GPIO_IRQ_TYPE0      0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define GPIO_IRQ_TYPE1      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define GPIO_IRQ_TYPE2      0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GPIO_IRQ_STATUS     0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				     const struct aspeed_sgpio_bank *bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				     const enum aspeed_sgpio_reg reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case reg_val:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return gpio->base + bank->val_regs + GPIO_VAL_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	case reg_rdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		return gpio->base + bank->rdata_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	case reg_irq_enable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	case reg_irq_type0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case reg_irq_type1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case reg_irq_type2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	case reg_irq_status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		/* acturally if code runs to here, it's an error case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPIO_BANK(x)    ((x % SGPIO_OUTPUT_OFFSET) >> 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPIO_OFFSET(x)  ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPIO_BIT(x)     BIT(GPIO_OFFSET(x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bank = GPIO_BANK(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	WARN_ON(bank >= ARRAY_SIZE(aspeed_sgpio_banks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return &aspeed_sgpio_banks[bank];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		unsigned long *valid_mask, unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int n = sgpio->n_sgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int c = SGPIO_OUTPUT_OFFSET - n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	/* input GPIOs in the lower range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	bitmap_set(valid_mask, 0, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	bitmap_clear(valid_mask, n, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* output GPIOS above SGPIO_OUTPUT_OFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		unsigned long *valid_mask, unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	int n = sgpio->n_sgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* input GPIOs in the lower range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	bitmap_set(valid_mask, 0, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	bitmap_clear(valid_mask, n, ngpios - n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static bool aspeed_sgpio_is_input(unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	return offset < SGPIO_OUTPUT_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const struct aspeed_sgpio_bank *bank = to_bank(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	enum aspeed_sgpio_reg reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	reg = aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	rc = !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int sgpio_set_value(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	const struct aspeed_sgpio_bank *bank = to_bank(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	void __iomem *addr_r, *addr_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (aspeed_sgpio_is_input(offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	/* Since this is an output, read the cached value from rdata, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	 * update val. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	addr_r = bank_reg(gpio, bank, reg_rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	addr_w = bank_reg(gpio, bank, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	reg = ioread32(addr_r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		reg |= GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		reg &= ~GPIO_BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	iowrite32(reg, addr_w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	sgpio_set_value(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	return aspeed_sgpio_is_input(offset) ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct aspeed_sgpio *gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* No special action is required for setting the direction; we'll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * error-out in sgpio_set_value if this isn't an output GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	rc = sgpio_set_value(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int aspeed_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return !!aspeed_sgpio_is_input(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static void irqd_to_aspeed_sgpio_data(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 					struct aspeed_sgpio **gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 					const struct aspeed_sgpio_bank **bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 					u32 *bit, int *offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct aspeed_sgpio *internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	*offset = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	internal = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	WARN_ON(!internal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	*gpio = internal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	*bank = to_bank(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	*bit = GPIO_BIT(*offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void aspeed_sgpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	const struct aspeed_sgpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct aspeed_sgpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	void __iomem *status_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	u32 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	status_addr = bank_reg(gpio, bank, reg_irq_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	iowrite32(bit, status_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	const struct aspeed_sgpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct aspeed_sgpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	u32 reg, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	addr = bank_reg(gpio, bank, reg_irq_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	reg = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		reg |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		reg &= ~bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	iowrite32(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static void aspeed_sgpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	aspeed_sgpio_irq_set_mask(d, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void aspeed_sgpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	aspeed_sgpio_irq_set_mask(d, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static int aspeed_sgpio_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	u32 type0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	u32 type1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	u32 type2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	u32 bit, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	const struct aspeed_sgpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	irq_flow_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct aspeed_sgpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	irqd_to_aspeed_sgpio_data(d, &gpio, &bank, &bit, &offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	switch (type & IRQ_TYPE_SENSE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		type2 |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		type0 |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		type0 |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		type1 |= bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	spin_lock_irqsave(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	addr = bank_reg(gpio, bank, reg_irq_type0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	reg = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	reg = (reg & ~bit) | type0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	iowrite32(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	addr = bank_reg(gpio, bank, reg_irq_type1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	reg = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	reg = (reg & ~bit) | type1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	iowrite32(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	addr = bank_reg(gpio, bank, reg_irq_type2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	reg = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	reg = (reg & ~bit) | type2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	iowrite32(reg, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	spin_unlock_irqrestore(&gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	irq_set_handler_locked(d, handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	struct irq_chip *ic = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	struct aspeed_sgpio *data = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	unsigned int i, p, girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	chained_irq_enter(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		const struct aspeed_sgpio_bank *bank = &aspeed_sgpio_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		reg = ioread32(bank_reg(data, bank, reg_irq_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		for_each_set_bit(p, &reg, 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			girq = irq_find_mapping(gc->irq.domain, i * 32 + p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			generic_handle_irq(girq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	chained_irq_exit(ic, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct irq_chip aspeed_sgpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	.name       = "aspeed-sgpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.irq_ack    = aspeed_sgpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	.irq_mask   = aspeed_sgpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.irq_unmask = aspeed_sgpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	.irq_set_type   = aspeed_sgpio_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				   struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	int rc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	const struct aspeed_sgpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	struct gpio_irq_chip *irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	rc = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	gpio->irq = rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		bank =  &aspeed_sgpio_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		/* disable irq enable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_enable));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		/* clear status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	irq = &gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	irq->chip = &aspeed_sgpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	irq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	irq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	irq->parent_handler = aspeed_sgpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	irq->parent_handler_data = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	irq->parents = &gpio->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	irq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	/* Apply default IRQ settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	for (i = 0; i < ARRAY_SIZE(aspeed_sgpio_banks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		bank = &aspeed_sgpio_banks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		/* set falling or level-low irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		/* trigger type is edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		/* single edge trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		iowrite32(0x00000000, bank_reg(gpio, bank, reg_irq_type2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static const struct of_device_id aspeed_sgpio_of_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	{ .compatible = "aspeed,ast2400-sgpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	{ .compatible = "aspeed,ast2500-sgpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int __init aspeed_sgpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct aspeed_sgpio *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	u32 nr_gpios, sgpio_freq, sgpio_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	unsigned long apb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	if (!gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	gpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	if (IS_ERR(gpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return PTR_ERR(gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		dev_err(&pdev->dev, "Could not read ngpios property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	} else if (nr_gpios > MAX_NR_HW_SGPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			MAX_NR_HW_SGPIO, nr_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	gpio->n_sgpio = nr_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		dev_err(&pdev->dev, "Could not read bus-frequency property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	gpio->pclk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	if (IS_ERR(gpio->pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		dev_err(&pdev->dev, "devm_clk_get failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return PTR_ERR(gpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	apb_freq = clk_get_rate(gpio->pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	 * From the datasheet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	 *	SGPIO period = 1/PCLK * 2 * (GPIO254[31:16] + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	 *	period = 2 * (GPIO254[31:16] + 1) / PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	 *	frequency = 1 / (2 * (GPIO254[31:16] + 1) / PCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	 *	frequency = PCLK / (2 * (GPIO254[31:16] + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	 *	frequency * 2 * (GPIO254[31:16] + 1) = PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	 *	GPIO254[31:16] = PCLK / (frequency * 2) - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	if (sgpio_freq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	sgpio_clk_div = (apb_freq / (sgpio_freq * 2)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	if (sgpio_clk_div > (1 << 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 		  FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		  ASPEED_SGPIO_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 		  gpio->base + ASPEED_SGPIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	spin_lock_init(&gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	gpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	gpio->chip.direction_input = aspeed_sgpio_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	gpio->chip.direction_output = aspeed_sgpio_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	gpio->chip.get_direction = aspeed_sgpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	gpio->chip.request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	gpio->chip.free = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	gpio->chip.get = aspeed_sgpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	gpio->chip.set = aspeed_sgpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	gpio->chip.set_config = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	gpio->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	aspeed_sgpio_setup_irqs(gpio, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct platform_driver aspeed_sgpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 		.name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 		.of_match_table = aspeed_sgpio_of_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) module_platform_driver_probe(aspeed_sgpio_driver, aspeed_sgpio_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_DESCRIPTION("Aspeed Serial GPIO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MODULE_LICENSE("GPL");