^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * GPIO driver for the AMD G series FCH (eg. GX-412TC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 metux IT consult
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Enrico Weigelt, metux IT consult <info@metux.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_data/gpio/gpio-amd-fch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AMD_FCH_MMIO_BASE 0xFED80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define AMD_FCH_GPIO_BANK0_BASE 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AMD_FCH_GPIO_SIZE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AMD_FCH_GPIO_FLAG_DIRECTION BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AMD_FCH_GPIO_FLAG_WRITE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AMD_FCH_GPIO_FLAG_READ BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const struct resource amd_fch_gpio_iores =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_RES_MEM_NAMED(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) AMD_FCH_MMIO_BASE + AMD_FCH_GPIO_BANK0_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) AMD_FCH_GPIO_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "amd-fch-gpio-iomem");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct amd_fch_gpio_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct gpio_chip gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct amd_fch_gpio_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void __iomem *amd_fch_gpio_addr(struct amd_fch_gpio_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return priv->base + priv->pdata->gpio_reg[gpio]*sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int amd_fch_gpio_direction_input(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel_relaxed(readl_relaxed(ptr) & ~AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int amd_fch_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val = readl_relaxed(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val |= AMD_FCH_GPIO_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val &= ~AMD_FCH_GPIO_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel_relaxed(val | AMD_FCH_GPIO_FLAG_DIRECTION, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static int amd_fch_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_DIRECTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void amd_fch_gpio_set(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) void __iomem *ptr = amd_fch_gpio_addr(priv, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mask = readl_relaxed(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mask |= AMD_FCH_GPIO_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mask &= ~AMD_FCH_GPIO_FLAG_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) writel_relaxed(mask, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int amd_fch_gpio_get(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct amd_fch_gpio_priv *priv = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) void __iomem *ptr = amd_fch_gpio_addr(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ret = (readl_relaxed(ptr) & AMD_FCH_GPIO_FLAG_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int amd_fch_gpio_request(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int gpio_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int amd_fch_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct amd_fch_gpio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct amd_fch_gpio_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(&pdev->dev, "no platform_data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) priv->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) priv->gc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) priv->gc.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) priv->gc.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) priv->gc.ngpio = priv->pdata->gpio_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) priv->gc.names = priv->pdata->gpio_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) priv->gc.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) priv->gc.request = amd_fch_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) priv->gc.direction_input = amd_fch_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) priv->gc.direction_output = amd_fch_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) priv->gc.get_direction = amd_fch_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) priv->gc.get = amd_fch_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) priv->gc.set = amd_fch_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) priv->base = devm_ioremap_resource(&pdev->dev, &amd_fch_gpio_iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return devm_gpiochip_add_data(&pdev->dev, &priv->gc, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct platform_driver amd_fch_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = AMD_FCH_GPIO_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .probe = amd_fch_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) module_platform_driver(amd_fch_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MODULE_DESCRIPTION("AMD G-series FCH GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODULE_ALIAS("platform:" AMD_FCH_GPIO_DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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