Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2013 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Based on gpio-mpc8xxx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_gpio.h> /* For of_mm_gpio_chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define ALTERA_GPIO_MAX_NGPIO		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define ALTERA_GPIO_DATA		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define ALTERA_GPIO_DIR			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define ALTERA_GPIO_IRQ_MASK		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define ALTERA_GPIO_EDGE_CAP		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) * struct altera_gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) * @mmchip		: memory mapped chip structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) * @gpio_lock		: synchronization lock so that new irq/set/get requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) *			  will be blocked until the current one completes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) * @interrupt_trigger	: specifies the hardware configured IRQ trigger type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) *			  (rising, falling, both, high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) * @mapped_irq		: kernel mapped irq number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) * @irq_chip		: IRQ chip configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct altera_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct of_mm_gpio_chip mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	raw_spinlock_t gpio_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	int interrupt_trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	int mapped_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static void altera_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mm_gc = &altera_gc->mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* Set ALTERA_GPIO_IRQ_MASK bit to unmask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	intmask |= BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void altera_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 intmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	mm_gc = &altera_gc->mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	raw_spin_lock_irqsave(&altera_gc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	intmask = readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Clear ALTERA_GPIO_IRQ_MASK bit to mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	intmask &= ~BIT(irqd_to_hwirq(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	writel(intmask, mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	raw_spin_unlock_irqrestore(&altera_gc->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * This controller's IRQ type is synthesized in hardware, so this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * just checks if the requested set_type matches the synthesized IRQ type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int altera_gpio_irq_set_type(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				   unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	altera_gc = gpiochip_get_data(irq_data_get_irq_chip_data(d));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (type == IRQ_TYPE_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		irq_set_handler_locked(d, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (type == altera_gc->interrupt_trigger) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (type == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			irq_set_handler_locked(d, handle_simple_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	irq_set_handler_locked(d, handle_bad_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static unsigned int altera_gpio_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	altera_gpio_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int altera_gpio_get(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return !!(readl(mm_gc->regs + ALTERA_GPIO_DATA) & BIT(offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void altera_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct altera_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	unsigned int data_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		data_reg |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		data_reg &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int altera_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct altera_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	unsigned int gpio_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	/* Set pin as input, assumes software controlled IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	gpio_ddr &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int altera_gpio_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	struct altera_gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	unsigned int data_reg, gpio_ddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	raw_spin_lock_irqsave(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/* Sets the GPIO value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	data_reg = readl(mm_gc->regs + ALTERA_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		data_reg |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		data_reg &= ~BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	writel(data_reg, mm_gc->regs + ALTERA_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* Set pin as output, assumes software controlled IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	gpio_ddr = readl(mm_gc->regs + ALTERA_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	gpio_ddr |= BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	writel(gpio_ddr, mm_gc->regs + ALTERA_GPIO_DIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	raw_spin_unlock_irqrestore(&chip->gpio_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static void altera_gpio_irq_edge_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	mm_gc = &altera_gc->mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	irqdomain = altera_gc->mmchip.gc.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	while ((status =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	      (readl(mm_gc->regs + ALTERA_GPIO_EDGE_CAP) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	      readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		writel(status, mm_gc->regs + ALTERA_GPIO_EDGE_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			generic_handle_irq(irq_find_mapping(irqdomain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void altera_gpio_irq_leveL_high_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct irq_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct irq_domain *irqdomain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	altera_gc = gpiochip_get_data(irq_desc_get_handler_data(desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mm_gc = &altera_gc->mmchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	irqdomain = altera_gc->mmchip.gc.irq.domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	status = readl(mm_gc->regs + ALTERA_GPIO_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	status &= readl(mm_gc->regs + ALTERA_GPIO_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	for_each_set_bit(i, &status, mm_gc->gc.ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		generic_handle_irq(irq_find_mapping(irqdomain, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int altera_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int reg, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	struct altera_gpio_chip *altera_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	altera_gc = devm_kzalloc(&pdev->dev, sizeof(*altera_gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!altera_gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	raw_spin_lock_init(&altera_gc->gpio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (of_property_read_u32(node, "altr,ngpio", &reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		/* By default assume maximum ngpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		altera_gc->mmchip.gc.ngpio = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (altera_gc->mmchip.gc.ngpio > ALTERA_GPIO_MAX_NGPIO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		dev_warn(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			"ngpio is greater than %d, defaulting to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			ALTERA_GPIO_MAX_NGPIO, ALTERA_GPIO_MAX_NGPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		altera_gc->mmchip.gc.ngpio = ALTERA_GPIO_MAX_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	altera_gc->mmchip.gc.direction_input	= altera_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	altera_gc->mmchip.gc.direction_output	= altera_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	altera_gc->mmchip.gc.get		= altera_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	altera_gc->mmchip.gc.set		= altera_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	altera_gc->mmchip.gc.owner		= THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	altera_gc->mmchip.gc.parent		= &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	altera_gc->mapped_irq = platform_get_irq_optional(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (altera_gc->mapped_irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		goto skip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (of_property_read_u32(node, "altr,interrupt-type", &reg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			"altr,interrupt-type value not set in device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	altera_gc->interrupt_trigger = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	altera_gc->irq_chip.name = "altera-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	altera_gc->irq_chip.irq_mask     = altera_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	altera_gc->irq_chip.irq_unmask   = altera_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	altera_gc->irq_chip.irq_set_type = altera_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	altera_gc->irq_chip.irq_startup  = altera_gpio_irq_startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	altera_gc->irq_chip.irq_shutdown = altera_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	girq = &altera_gc->mmchip.gc.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	girq->chip = &altera_gc->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (altera_gc->interrupt_trigger == IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		girq->parent_handler = altera_gpio_irq_leveL_high_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		girq->parent_handler = altera_gpio_irq_edge_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	girq->parents[0] = altera_gc->mapped_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) skip_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	ret = of_mm_gpiochip_add_data(node, &altera_gc->mmchip, altera_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		dev_err(&pdev->dev, "Failed adding memory mapped gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	platform_set_drvdata(pdev, altera_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int altera_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	struct altera_gpio_chip *altera_gc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	of_mm_gpiochip_remove(&altera_gc->mmchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const struct of_device_id altera_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	{ .compatible = "altr,pio-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MODULE_DEVICE_TABLE(of, altera_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct platform_driver altera_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		.name	= "altera_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		.of_match_table = of_match_ptr(altera_gpio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.probe		= altera_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	.remove		= altera_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int __init altera_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return platform_driver_register(&altera_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) subsys_initcall(altera_gpio_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void __exit altera_gpio_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	platform_driver_unregister(&altera_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) module_exit(altera_gpio_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MODULE_AUTHOR("Tien Hock Loh <thloh@altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MODULE_DESCRIPTION("Altera GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MODULE_LICENSE("GPL");