^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011-2012 Avionic Design GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GPIO_DDR(gpio) (0x00 << (gpio)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GPIO_PLR(gpio) (0x01 << (gpio)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GPIO_IER(gpio) (0x02 << (gpio)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GPIO_ISR(gpio) (0x03 << (gpio)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GPIO_PTR(gpio) (0x04 << (gpio)->reg_shift)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct adnp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct gpio_chip gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unsigned int reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct mutex i2c_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct mutex irq_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 *irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u8 *irq_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 *irq_rise;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u8 *irq_fall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 *irq_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u8 *irq_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static int adnp_read(struct adnp *adnp, unsigned offset, uint8_t *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) err = i2c_smbus_read_byte_data(adnp->client, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dev_err(adnp->gpio.parent, "%s failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "i2c_smbus_read_byte_data()", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *value = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int adnp_write(struct adnp *adnp, unsigned offset, uint8_t value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) err = i2c_smbus_write_byte_data(adnp->client, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(adnp->gpio.parent, "%s failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "i2c_smbus_write_byte_data()", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int adnp_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct adnp *adnp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int reg = offset >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int pos = offset & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return (value & BIT(pos)) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static void __adnp_gpio_set(struct adnp *adnp, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int reg = offset >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int pos = offset & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) err = adnp_read(adnp, GPIO_PLR(adnp) + reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) adnp_write(adnp, GPIO_PLR(adnp) + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void adnp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct adnp *adnp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __adnp_gpio_set(adnp, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int adnp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct adnp *adnp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int reg = offset >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int pos = offset & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) value &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) err = adnp_write(adnp, GPIO_DDR(adnp) + reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (value & BIT(pos)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) err = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int adnp_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct adnp *adnp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int reg = offset >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int pos = offset & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err = adnp_write(adnp, GPIO_DDR(adnp) + reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) err = adnp_read(adnp, GPIO_DDR(adnp) + reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!(val & BIT(pos))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) err = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) __adnp_gpio_set(adnp, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void adnp_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct adnp *adnp = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int num_regs = 1 << adnp->reg_shift, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 ddr, plr, ier, isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) err = adnp_read(adnp, GPIO_DDR(adnp) + i, &ddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) err = adnp_read(adnp, GPIO_PLR(adnp) + i, &plr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) for (j = 0; j < 8; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int bit = (i << adnp->reg_shift) + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const char *direction = "input ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const char *level = "low ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const char *interrupt = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const char *pending = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ddr & BIT(j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) direction = "output";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (plr & BIT(j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) level = "high";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ier & BIT(j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) interrupt = "enabled ";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (isr & BIT(j))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pending = "pending";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) seq_printf(s, "%2u: %s %s IRQ %s %s\n", bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) direction, level, interrupt, pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static irqreturn_t adnp_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct adnp *adnp = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int num_regs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) num_regs = 1 << adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int base = i << adnp->reg_shift, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u8 changed, level, isr, ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) err = adnp_read(adnp, GPIO_PLR(adnp) + i, &level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err = adnp_read(adnp, GPIO_ISR(adnp) + i, &isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) err = adnp_read(adnp, GPIO_IER(adnp) + i, &ier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* determine pins that changed levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) changed = level ^ adnp->irq_level[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* compute edge-triggered interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pending = changed & ((adnp->irq_fall[i] & ~level) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (adnp->irq_rise[i] & level));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* add in level-triggered interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pending |= (adnp->irq_high[i] & level) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) (adnp->irq_low[i] & ~level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* mask out non-pending and disabled interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pending &= isr & ier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) for_each_set_bit(bit, &pending, 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) unsigned int child_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) child_irq = irq_find_mapping(adnp->gpio.irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) base + bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) handle_nested_irq(child_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void adnp_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct adnp *adnp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int reg = d->hwirq >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int pos = d->hwirq & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) adnp->irq_enable[reg] &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void adnp_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct adnp *adnp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int reg = d->hwirq >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int pos = d->hwirq & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) adnp->irq_enable[reg] |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int adnp_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct adnp *adnp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int reg = d->hwirq >> adnp->reg_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned int pos = d->hwirq & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) adnp->irq_rise[reg] |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) adnp->irq_rise[reg] &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) adnp->irq_fall[reg] |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) adnp->irq_fall[reg] &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (type & IRQ_TYPE_LEVEL_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) adnp->irq_high[reg] |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) adnp->irq_high[reg] &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (type & IRQ_TYPE_LEVEL_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) adnp->irq_low[reg] |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) adnp->irq_low[reg] &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void adnp_irq_bus_lock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct adnp *adnp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mutex_lock(&adnp->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void adnp_irq_bus_unlock(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct adnp *adnp = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int num_regs = 1 << adnp->reg_shift, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mutex_lock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) for (i = 0; i < num_regs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) adnp_write(adnp, GPIO_IER(adnp) + i, adnp->irq_enable[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mutex_unlock(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mutex_unlock(&adnp->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct irq_chip adnp_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .name = "gpio-adnp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .irq_mask = adnp_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .irq_unmask = adnp_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .irq_set_type = adnp_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .irq_bus_lock = adnp_irq_bus_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .irq_bus_sync_unlock = adnp_irq_bus_unlock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int adnp_irq_setup(struct adnp *adnp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int num_regs = 1 << adnp->reg_shift, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct gpio_chip *chip = &adnp->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mutex_init(&adnp->irq_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * Allocate memory to keep track of the current level and trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * modes of the interrupts. To avoid multiple allocations, a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * large buffer is allocated and pointers are setup to point at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * corresponding offsets. For consistency, the layout of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * is chosen to match the register layout of the hardware in that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * each segment contains the corresponding bits for all interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) adnp->irq_enable = devm_kcalloc(chip->parent, num_regs, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!adnp->irq_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) adnp->irq_level = adnp->irq_enable + (num_regs * 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) adnp->irq_rise = adnp->irq_enable + (num_regs * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) adnp->irq_fall = adnp->irq_enable + (num_regs * 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) adnp->irq_high = adnp->irq_enable + (num_regs * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) adnp->irq_low = adnp->irq_enable + (num_regs * 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < num_regs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * Read the initial level of all pins to allow the emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * of edge triggered interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) err = adnp_read(adnp, GPIO_PLR(adnp) + i, &adnp->irq_level[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) err = adnp_write(adnp, GPIO_IER(adnp) + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) adnp->irq_enable[i] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err = devm_request_threaded_irq(chip->parent, adnp->client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) NULL, adnp_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_name(chip->parent), adnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (err != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(chip->parent, "can't request IRQ#%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) adnp->client->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int adnp_gpio_setup(struct adnp *adnp, unsigned int num_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) bool is_irq_controller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct gpio_chip *chip = &adnp->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) adnp->reg_shift = get_count_order(num_gpios) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) chip->direction_input = adnp_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) chip->direction_output = adnp_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) chip->get = adnp_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) chip->set = adnp_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) chip->can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (IS_ENABLED(CONFIG_DEBUG_FS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) chip->dbg_show = adnp_gpio_dbg_show;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) chip->ngpio = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) chip->label = adnp->client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) chip->parent = &adnp->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) chip->of_node = chip->parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (is_irq_controller) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) err = adnp_irq_setup(adnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) girq->chip = &adnp_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) girq->threaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err = devm_gpiochip_add_data(&adnp->client->dev, chip, adnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int adnp_i2c_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct device_node *np = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct adnp *adnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) err = of_property_read_u32(np, "nr-gpios", &num_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) client->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!adnp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mutex_init(&adnp->i2c_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) adnp->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) err = adnp_gpio_setup(adnp, num_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) of_property_read_bool(np, "interrupt-controller"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) i2c_set_clientdata(client, adnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const struct i2c_device_id adnp_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { "gpio-adnp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_DEVICE_TABLE(i2c, adnp_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static const struct of_device_id adnp_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { .compatible = "ad,gpio-adnp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MODULE_DEVICE_TABLE(of, adnp_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static struct i2c_driver adnp_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "gpio-adnp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .of_match_table = adnp_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .probe = adnp_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .id_table = adnp_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) module_i2c_driver(adnp_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DESCRIPTION("Avionic Design N-bit GPIO expander");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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