^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 74Hx164 - Generic serial-in/parallel-out 8-bits shift register GPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 Miguel Gaio <miguel.gaio@efixo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GEN_74X164_NUMBER_GPIOS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct gen_74x164_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct gpio_desc *gpiod_oe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Since the registers are chained, every byte sent will make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * the previous byte shift to the next register in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * chain. Thus, the first byte sent will end up in the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * register at the end of the transfer. So, to have a logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * numbering, store the bytes in reverse order.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u8 buffer[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int __gen_74x164_write_config(struct gen_74x164_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return spi_write(to_spi_device(chip->gpio_chip.parent), chip->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) chip->registers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int gen_74x164_get_value(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct gen_74x164_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 bank = chip->registers - 1 - offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 pin = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ret = (chip->buffer[bank] >> pin) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void gen_74x164_set_value(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct gen_74x164_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 bank = chip->registers - 1 - offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 pin = offset % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) chip->buffer[bank] |= (1 << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) chip->buffer[bank] &= ~(1 << pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __gen_74x164_write_config(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void gen_74x164_set_multiple(struct gpio_chip *gc, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct gen_74x164_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long bankmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) size_t bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mutex_lock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) bank = chip->registers - 1 - offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) bitmask = bitmap_get_value8(bits, offset) & bankmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) chip->buffer[bank] &= ~bankmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) chip->buffer[bank] |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __gen_74x164_write_config(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mutex_unlock(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static int gen_74x164_direction_output(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) gen_74x164_set_value(gc, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int gen_74x164_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct gen_74x164_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * bits_per_word cannot be configured in platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) spi->bits_per_word = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = spi_setup(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = device_property_read_u32(&spi->dev, "registers-number", &nregs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(&spi->dev, "Missing 'registers-number' property.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) chip = devm_kzalloc(&spi->dev, sizeof(*chip) + nregs, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) chip->gpiod_oe = devm_gpiod_get_optional(&spi->dev, "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (IS_ERR(chip->gpiod_oe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return PTR_ERR(chip->gpiod_oe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) gpiod_set_value_cansleep(chip->gpiod_oe, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spi_set_drvdata(spi, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) chip->gpio_chip.label = spi->modalias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) chip->gpio_chip.direction_output = gen_74x164_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) chip->gpio_chip.get = gen_74x164_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) chip->gpio_chip.set = gen_74x164_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) chip->gpio_chip.set_multiple = gen_74x164_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) chip->gpio_chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) chip->registers = nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) chip->gpio_chip.can_sleep = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) chip->gpio_chip.parent = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) chip->gpio_chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mutex_init(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = __gen_74x164_write_config(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_err(&spi->dev, "Failed writing: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) goto exit_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = gpiochip_add_data(&chip->gpio_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) exit_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mutex_destroy(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int gen_74x164_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct gen_74x164_chip *chip = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gpiod_set_value_cansleep(chip->gpiod_oe, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gpiochip_remove(&chip->gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) mutex_destroy(&chip->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct of_device_id gen_74x164_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .compatible = "fairchild,74hc595" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .compatible = "nxp,74lvc594" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MODULE_DEVICE_TABLE(of, gen_74x164_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct spi_driver gen_74x164_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .name = "74x164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .of_match_table = gen_74x164_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .probe = gen_74x164_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .remove = gen_74x164_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) module_spi_driver(gen_74x164_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MODULE_AUTHOR("Miguel Gaio <miguel.gaio@efixo.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MODULE_DESCRIPTION("GPIO expander driver for 74X164 8-bits shift register");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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