^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for the ACCES 104-IDIO-16 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2015 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This driver supports the following ACCES devices: 104-IDIO-16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IDIO_16_EXTENT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static unsigned int base[MAX_NUM_IDIO_16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static unsigned int num_idio_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param_hw_array(base, uint, ioport, &num_idio_16, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(base, "ACCES 104-IDIO-16 base addresses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned int irq[MAX_NUM_IDIO_16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) module_param_hw_array(irq, uint, irq, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * struct idio_16_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @lock: synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @irq_mask: I/O bits affected by interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @base: base port address of the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @out_state: output bits state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct idio_16_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned out_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int idio_16_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (offset > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int idio_16_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int idio_16_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) chip->set(chip, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int idio_16_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) const unsigned mask = BIT(offset-16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (offset < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (offset < 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return !!(inb(idio16gpio->base + 1) & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return !!(inb(idio16gpio->base + 5) & (mask>>8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (*mask & GENMASK(23, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) *bits |= (unsigned long)inb(idio16gpio->base + 1) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (*mask & GENMASK(31, 24))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *bits |= (unsigned long)inb(idio16gpio->base + 5) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void idio_16_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const unsigned mask = BIT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (offset > 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) idio16gpio->out_state |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) idio16gpio->out_state &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (offset > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) outb(idio16gpio->out_state, idio16gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) idio16gpio->out_state &= ~*mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) idio16gpio->out_state |= *mask & *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (*mask & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) outb(idio16gpio->out_state, idio16gpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if ((*mask >> 8) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) outb(idio16gpio->out_state >> 8, idio16gpio->base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void idio_16_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void idio_16_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const unsigned long mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) idio16gpio->irq_mask &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!idio16gpio->irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) outb(0, idio16gpio->base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static void idio_16_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const unsigned long mask = BIT(irqd_to_hwirq(data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const unsigned long prev_irq_mask = idio16gpio->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) idio16gpio->irq_mask |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!prev_irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) raw_spin_lock_irqsave(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) inb(idio16gpio->base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int idio_16_irq_set_type(struct irq_data *data, unsigned flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* The only valid irq types are none and both-edges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (flow_type != IRQ_TYPE_NONE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct irq_chip idio_16_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .name = "104-idio-16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .irq_ack = idio_16_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .irq_mask = idio_16_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .irq_unmask = idio_16_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .irq_set_type = idio_16_irq_set_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct idio_16_gpio *const idio16gpio = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct gpio_chip *const chip = &idio16gpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) generic_handle_irq(irq_find_mapping(chip->irq.domain, gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) raw_spin_lock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) outb(0, idio16gpio->base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) raw_spin_unlock(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IDIO_16_NGPIO 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const char *idio_16_names[IDIO_16_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int idio_16_irq_init_hw(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Disable IRQ by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) outb(0, idio16gpio->base + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) outb(0, idio16gpio->base + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static int idio_16_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct idio_16_gpio *idio16gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const char *const name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!idio16gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) base[id], base[id] + IDIO_16_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) idio16gpio->chip.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) idio16gpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) idio16gpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) idio16gpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) idio16gpio->chip.ngpio = IDIO_16_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) idio16gpio->chip.names = idio_16_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) idio16gpio->chip.get = idio_16_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) idio16gpio->chip.set = idio_16_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) idio16gpio->base = base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) idio16gpio->out_state = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) girq = &idio16gpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) girq->chip = &idio_16_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) girq->init_hw = idio_16_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) raw_spin_lock_init(&idio16gpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) idio16gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "IRQ handler registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct isa_driver idio_16_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .probe = idio_16_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .name = "104-idio-16"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) module_isa_driver(idio_16_driver, num_idio_16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MODULE_DESCRIPTION("ACCES 104-IDIO-16 GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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