^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * GPIO driver for the ACCES 104-DIO-48E series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2016 William Breathitt Gray
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This driver supports the following ACCES devices: 104-DIO-48E and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 104-DIO-24E.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqdesc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/isa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DIO48E_EXTENT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static unsigned int base[MAX_NUM_DIO48E];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static unsigned int num_dio48e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static unsigned int irq[MAX_NUM_DIO48E];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param_hw_array(irq, uint, irq, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * struct dio48e_gpio - GPIO device private data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @chip: instance of the gpio_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @io_state: bit I/O state (whether bit is set to input or output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @out_state: output bits state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @control: Control registers state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @lock: synchronization lock to prevent I/O race conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @base: base port address of the GPIO device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @irq_mask: I/O bits affected by interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct dio48e_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned char io_state[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned char out_state[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned char control[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned char irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const unsigned port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const unsigned mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (dio48egpio->io_state[port] & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const unsigned io_port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) const unsigned int control_port = io_port / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Check if configuring Port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if (io_port == 2 || io_port == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Port C can be configured by nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (offset % 8 > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) dio48egpio->io_state[io_port] |= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dio48egpio->control[control_port] |= BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dio48egpio->io_state[io_port] |= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dio48egpio->control[control_port] |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dio48egpio->io_state[io_port] |= 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (io_port == 0 || io_port == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dio48egpio->control[control_port] |= BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dio48egpio->control[control_port] |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) control = BIT(7) | dio48egpio->control[control_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) control &= ~BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const unsigned io_port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) const unsigned int control_port = io_port / 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const unsigned mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Check if configuring Port C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (io_port == 2 || io_port == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Port C can be configured by nibble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (offset % 8 > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dio48egpio->io_state[io_port] &= 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dio48egpio->control[control_port] &= ~BIT(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dio48egpio->io_state[io_port] &= 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) dio48egpio->control[control_port] &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dio48egpio->io_state[io_port] &= 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (io_port == 0 || io_port == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dio48egpio->control[control_port] &= ~BIT(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dio48egpio->control[control_port] &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dio48egpio->out_state[io_port] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dio48egpio->out_state[io_port] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) control = BIT(7) | dio48egpio->control[control_port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) control &= ~BIT(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) outb(control, control_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const unsigned port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const unsigned mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const unsigned in_port = (port > 2) ? port + 1 : port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* ensure that GPIO is set for input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!(dio48egpio->io_state[port] & mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) port_state = inb(dio48egpio->base + in_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return !!(port_state & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned long port_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* clear bits array to a clean slate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bitmap_zero(bits, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) port_addr = dio48egpio->base + ports[offset / 8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) port_state = inb(port_addr) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bitmap_set_value8(bits, port_state, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const unsigned port = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) const unsigned mask = BIT(offset % 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const unsigned out_port = (port > 2) ? port + 1 : port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dio48egpio->out_state[port] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) dio48egpio->out_state[port] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned long *mask, unsigned long *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) unsigned long gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) size_t index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int port_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) unsigned long bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) index = offset / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) port_addr = dio48egpio->base + ports[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* update output state data and set device gpio register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dio48egpio->out_state[index] &= ~gpio_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dio48egpio->out_state[index] |= bitmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) outb(dio48egpio->out_state[index], port_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void dio48e_irq_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void dio48e_irq_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) const unsigned long offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* only bit 3 on each respective Port C supports interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (offset != 19 && offset != 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (offset == 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dio48egpio->irq_mask &= ~BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dio48egpio->irq_mask &= ~BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!dio48egpio->irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) inb(dio48egpio->base + 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void dio48e_irq_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const unsigned long offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* only bit 3 on each respective Port C supports interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (offset != 19 && offset != 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) raw_spin_lock_irqsave(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!dio48egpio->irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) outb(0x00, dio48egpio->base + 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) outb(0x00, dio48egpio->base + 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (offset == 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dio48egpio->irq_mask |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dio48egpio->irq_mask |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const unsigned long offset = irqd_to_hwirq(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* only bit 3 on each respective Port C supports interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (offset != 19 && offset != 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static struct irq_chip dio48e_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "104-dio-48e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .irq_ack = dio48e_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .irq_mask = dio48e_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .irq_unmask = dio48e_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .irq_set_type = dio48e_irq_set_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct dio48e_gpio *const dio48egpio = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct gpio_chip *const chip = &dio48egpio->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) const unsigned long irq_mask = dio48egpio->irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned long gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) for_each_set_bit(gpio, &irq_mask, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) generic_handle_irq(irq_find_mapping(chip->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 19 + gpio*24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) raw_spin_lock(&dio48egpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) outb(0x00, dio48egpio->base + 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) raw_spin_unlock(&dio48egpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DIO48E_NGPIO 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const char *dio48e_names[DIO48E_NGPIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int dio48e_irq_init_hw(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Disable IRQ by default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) inb(dio48egpio->base + 0xB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int dio48e_probe(struct device *dev, unsigned int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct dio48e_gpio *dio48egpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const char *const name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!dio48egpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) base[id], base[id] + DIO48E_EXTENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dio48egpio->chip.label = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dio48egpio->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) dio48egpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dio48egpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dio48egpio->chip.ngpio = DIO48E_NGPIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dio48egpio->chip.names = dio48e_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dio48egpio->chip.get = dio48e_gpio_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dio48egpio->chip.set = dio48e_gpio_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dio48egpio->base = base[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) girq = &dio48egpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) girq->chip = &dio48e_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* This will let us handle the parent IRQ in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) girq->parent_handler = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) girq->num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) girq->parents = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) girq->handler = handle_edge_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) girq->init_hw = dio48e_irq_init_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) raw_spin_lock_init(&dio48egpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* initialize all GPIO as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) outb(0x80, base[id] + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) outb(0x00, base[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) outb(0x00, base[id] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) outb(0x00, base[id] + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) outb(0x00, base[id] + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) outb(0x80, base[id] + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) outb(0x00, base[id] + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) outb(0x00, base[id] + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) outb(0x00, base[id] + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) outb(0x00, base[id] + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dev, "GPIO registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dio48egpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(dev, "IRQ handler registering failed (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct isa_driver dio48e_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .probe = dio48e_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .name = "104-dio-48e"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) module_isa_driver(dio48e_driver, num_dio48e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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