^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FSI master definitions. These comprise the core <--> master interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * to allow the core to interact with the (hardware-specific) masters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) IBM Corporation 2016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef DRIVERS_FSI_MASTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DRIVERS_FSI_MASTER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Master registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * These are used by hardware masters, such as the one in the FSP2, AST2600 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the hub master in POWER processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FSI_MMODE 0x0 /* R/W: mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FSI_MDLYR 0x4 /* R/W: delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FSI_MCRSP 0x8 /* R/W: clock rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FSI_MENP0 0x10 /* R/W: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSI_MLEVP0 0x18 /* R: plug detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FSI_MSENP0 0x18 /* S: Set enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FSI_MCENP0 0x20 /* C: Clear enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FSI_MAEB 0x70 /* R: Error address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FSI_MVER 0x74 /* R: master version/type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FSI_MSTAP0 0xd0 /* R: Port status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FSI_MRESP0 0xd0 /* W: Port reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FSI_MESRB0 0x1d0 /* R: Master error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FSI_MRESB0 0x1d0 /* W: Reset bridge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FSI_MSCSB0 0x1d4 /* R: Master sub command stack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FSI_MATRB0 0x1d8 /* R: Master address trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FSI_MDTRB0 0x1dc /* R: Master data trace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FSI_MECTRL 0x2e0 /* W: Error control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* MMODE: Mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FSI_MMODE_RELA 0x20000000 /* Enable relative address commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* MSB=1, LSB=0 is 0.8 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* MSB=0, LSB=1 is 0.9 ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* MRESB: Reset brindge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define FSI_MRESB_RST_GEN 0x80000000 /* General reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* MRESP: Reset port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* MECTRL: Error control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* master 0 in error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define FSI_HUB_LINK_OFFSET 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define FSI_HUB_LINK_SIZE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FSI_HUB_MASTER_MAX_LINKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Protocol definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * These are used by low level masters that bit-bang out the protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Various protocol delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FSI_SEND_DELAY_CLOCKS 16 /* Number clocks for send delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FSI_INIT_CLOCKS 5000 /* Clock out any old data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define FSI_MASTER_DPOLL_CLOCKS 50 /* < 21 will cause slave to hang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define FSI_MASTER_EPOLL_CLOCKS 50 /* Number of clocks for E_POLL retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Various retry maximums */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define FSI_CRC_ERR_RETRIES 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define FSI_MASTER_MAX_BUSY 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define FSI_MASTER_MTOE_COUNT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Command encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define FSI_CMD_DPOLL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define FSI_CMD_EPOLL 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define FSI_CMD_TERM 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FSI_CMD_ABS_AR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define FSI_CMD_REL_AR 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define FSI_CMD_SAME_AR 0x3 /* but only a 2-bit opcode... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Slave responses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FSI_RESP_ACK 0 /* Success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FSI_RESP_BUSY 1 /* Slave busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FSI_RESP_ERRA 2 /* Any (misc) Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FSI_RESP_ERRC 3 /* Slave reports master CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FSI_CRC_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* fsi-master definition and flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FSI_MASTER_FLAG_SWCLOCK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Structures and function prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * These are common to all masters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct fsi_master {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int n_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mutex scan_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int (*read)(struct fsi_master *, int link, uint8_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) uint32_t addr, void *val, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int (*write)(struct fsi_master *, int link, uint8_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint32_t addr, const void *val, size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int (*term)(struct fsi_master *, int link, uint8_t id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int (*send_break)(struct fsi_master *, int link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int (*link_enable)(struct fsi_master *, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int (*link_config)(struct fsi_master *, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 t_send_delay, u8 t_echo_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define dev_to_fsi_master(d) container_of(d, struct fsi_master, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * fsi_master registration & lifetime: the fsi_master_register() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * fsi_master_unregister() functions will take ownership of the master, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * ->dev in particular. The registration path performs a get_device(), which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * takes the first reference on the device. Similarly, the unregistration path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * performs a put_device(), which may well drop the last reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * This means that master implementations *may* need to hold their own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * reference (via get_device()) on master->dev. In particular, if the device's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * ->release callback frees the fsi_master, then fsi_master_unregister will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * invoke this free if no other reference is held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * The same applies for the error path of fsi_master_register; if the call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * fails, dev->release will have been invoked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) extern int fsi_master_register(struct fsi_master *master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) extern void fsi_master_unregister(struct fsi_master *master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) extern int fsi_master_rescan(struct fsi_master *master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif /* DRIVERS_FSI_MASTER_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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