^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2018 IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * A FSI master controller, using a simple GPIO bit-banging interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/crc4.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/fsi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irqflags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/aspeed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/genalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "fsi-master.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "cf-fsi-fw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FW_FILE_NAME "cf-fsi-fw.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Common SCU based coprocessor control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCU_COPRO_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCU_COPRO_RESET 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCU_COPRO_CLK_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* AST2500 specific ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCU_2500_COPRO_SEG0 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCU_2500_COPRO_SEG1 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCU_2500_COPRO_SEG2 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SCU_2500_COPRO_SEG3 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SCU_2500_COPRO_SEG4 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SCU_2500_COPRO_SEG5 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SCU_2500_COPRO_SEG6 0x11c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SCU_2500_COPRO_SEG7 0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SCU_2500_COPRO_SEG8 0x124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SCU_2500_COPRO_SEG_SWAP 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SCU_2500_COPRO_CACHE_CTL 0x128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SCU_2500_COPRO_CACHE_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SCU_2500_COPRO_SEG0_CACHE_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SCU_2500_COPRO_SEG1_CACHE_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SCU_2500_COPRO_SEG2_CACHE_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SCU_2500_COPRO_SEG3_CACHE_EN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SCU_2500_COPRO_SEG4_CACHE_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SCU_2500_COPRO_SEG5_CACHE_EN 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SCU_2500_COPRO_SEG6_CACHE_EN 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SCU_2500_COPRO_SEG7_CACHE_EN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SCU_2500_COPRO_SEG8_CACHE_EN 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SCU_2400_COPRO_SEG0 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SCU_2400_COPRO_SEG2 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SCU_2400_COPRO_SEG4 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SCU_2400_COPRO_SEG6 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SCU_2400_COPRO_SEG8 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SCU_2400_COPRO_SEG_SWAP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SCU_2400_COPRO_CACHE_CTL 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SCU_2400_COPRO_CACHE_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SCU_2400_COPRO_SEG0_CACHE_EN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SCU_2400_COPRO_SEG2_CACHE_EN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SCU_2400_COPRO_SEG4_CACHE_EN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SCU_2400_COPRO_SEG6_CACHE_EN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SCU_2400_COPRO_SEG8_CACHE_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CVIC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CVIC_EN_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CVIC_TRIG_REG 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * System register base address (needed for configuring the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * coldfire maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SYSREG_BASE 0x1e600000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Amount of SRAM required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SRAM_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LAST_ADDR_INVALID 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct fsi_master_acf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct fsi_master master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regmap *scu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct mutex lock; /* mutex for command ordering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct gpio_desc *gpio_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct gpio_desc *gpio_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct gpio_desc *gpio_trans; /* Voltage translator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct gpio_desc *gpio_enable; /* FSI enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct gpio_desc *gpio_mux; /* Mux control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) uint16_t gpio_clk_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) uint16_t gpio_clk_dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) uint16_t gpio_dat_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) uint16_t gpio_dat_dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) uint16_t gpio_tra_vreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) uint16_t gpio_tra_dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) uint8_t gpio_clk_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) uint8_t gpio_dat_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) uint8_t gpio_tra_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) uint32_t cf_mem_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) size_t cf_mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *cf_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) void __iomem *cvic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gen_pool *sram_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) bool is_ast2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) bool external_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bool trace_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) uint32_t last_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) uint8_t t_send_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) uint8_t t_echo_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) uint32_t cvic_sw_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define to_fsi_master_acf(m) container_of(m, struct fsi_master_acf, master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct fsi_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) uint64_t msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) uint8_t bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CREATE_TRACE_POINTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #include <trace/events/fsi_master_ast_cf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void msg_push_bits(struct fsi_msg *msg, uint64_t data, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msg->msg <<= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) msg->msg |= data & ((1ull << bits) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) msg->bits += bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void msg_push_crc(struct fsi_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) uint8_t crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) top = msg->bits & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* start bit, and any non-aligned top bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* aligned bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) crc = crc4(crc, msg->msg, msg->bits - top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) msg_push_bits(msg, crc, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static void msg_finish_cmd(struct fsi_msg *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Left align message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cmd->msg <<= (64 - cmd->bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static bool check_same_address(struct fsi_master_acf *master, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) uint32_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* this will also handle LAST_ADDR_INVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return master->last_addr == (((id & 0x3) << 21) | (addr & ~0x3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static bool check_relative_address(struct fsi_master_acf *master, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint32_t addr, uint32_t *rel_addrp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint32_t last_addr = master->last_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int32_t rel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (last_addr == LAST_ADDR_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* We may be in 23-bit addressing mode, which uses the id as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * top two address bits. So, if we're referencing a different ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * use absolute addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (((last_addr >> 21) & 0x3) != id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* remove the top two bits from any 23-bit addressing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) last_addr &= (1 << 21) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* We know that the addresses are limited to 21 bits, so this won't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * overflow the signed rel_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rel_addr = addr - last_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (rel_addr > 255 || rel_addr < -256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *rel_addrp = (uint32_t)rel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void last_address_update(struct fsi_master_acf *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int id, bool valid, uint32_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (!valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) master->last_addr = LAST_ADDR_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) master->last_addr = ((id & 0x3) << 21) | (addr & ~0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Encode an Absolute/Relative/Same Address command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void build_ar_command(struct fsi_master_acf *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct fsi_msg *cmd, uint8_t id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) uint32_t addr, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int i, addr_bits, opcode_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bool write = !!data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) uint8_t ds, opcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) uint32_t rel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cmd->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) cmd->msg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* we have 21 bits of address max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) addr &= ((1 << 21) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* cmd opcodes are variable length - SAME_AR is only two bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) opcode_bits = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (check_same_address(master, id, addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* we still address the byte offset within the word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) addr_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) opcode_bits = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) opcode = FSI_CMD_SAME_AR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) trace_fsi_master_acf_cmd_same_addr(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else if (check_relative_address(master, id, addr, &rel_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* 8 bits plus sign */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) addr_bits = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) addr = rel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) opcode = FSI_CMD_REL_AR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) trace_fsi_master_acf_cmd_rel_addr(master, rel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) addr_bits = 21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) opcode = FSI_CMD_ABS_AR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) trace_fsi_master_acf_cmd_abs_addr(master, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * The read/write size is encoded in the lower bits of the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * (as it must be naturally-aligned), and the following ds bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * size addr:1 addr:0 ds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * 1 x x 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * 2 x 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * 4 0 1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ds = size > 1 ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) addr &= ~(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (size == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) addr |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) msg_push_bits(cmd, id, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) msg_push_bits(cmd, opcode, opcode_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) msg_push_bits(cmd, write ? 0 : 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) msg_push_bits(cmd, addr, addr_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) msg_push_bits(cmd, ds, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) for (i = 0; write && i < size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) msg_push_crc(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) msg_finish_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void build_dpoll_command(struct fsi_msg *cmd, uint8_t slave_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) cmd->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cmd->msg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) msg_push_bits(cmd, slave_id, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msg_push_bits(cmd, FSI_CMD_DPOLL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) msg_push_crc(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) msg_finish_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void build_epoll_command(struct fsi_msg *cmd, uint8_t slave_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) cmd->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) cmd->msg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) msg_push_bits(cmd, slave_id, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msg_push_bits(cmd, FSI_CMD_EPOLL, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) msg_push_crc(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) msg_finish_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void build_term_command(struct fsi_msg *cmd, uint8_t slave_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cmd->bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cmd->msg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) msg_push_bits(cmd, slave_id, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) msg_push_bits(cmd, FSI_CMD_TERM, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) msg_push_crc(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) msg_finish_cmd(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int do_copro_command(struct fsi_master_acf *master, uint32_t op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) uint32_t timeout = 10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) uint8_t stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) trace_fsi_master_acf_copro_command(master, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Send command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) iowrite32be(op, master->sram + CMD_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* Ring doorbell if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (master->cvic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Wait for status to indicate completion (or error) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (timeout-- == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_warn(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Timeout waiting for coprocessor completion\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) stat = ioread8(master->sram + CMD_STAT_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } while(stat < STAT_COMPLETE || stat == 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (stat == STAT_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) switch(stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case STAT_ERR_INVAL_CMD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case STAT_ERR_INVAL_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) case STAT_ERR_MTOE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return -ESHUTDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int clock_zeros(struct fsi_master_acf *master, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) while (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int rc, lcnt = min(count, 255);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rc = do_copro_command(master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CMD_IDLE_CLOCKS | (lcnt << CMD_REG_CLEN_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) count -= lcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int send_request(struct fsi_master_acf *master, struct fsi_msg *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) unsigned int resp_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) uint32_t op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) trace_fsi_master_acf_send_request(master, cmd, resp_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Store message into SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) iowrite32be((cmd->msg >> 32), master->sram + CMD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) iowrite32be((cmd->msg & 0xffffffff), master->sram + CMD_DATA + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) op = CMD_COMMAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) op |= cmd->bits << CMD_REG_CLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (resp_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) op |= resp_bits << CMD_REG_RLEN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return do_copro_command(master, op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int read_copro_response(struct fsi_master_acf *master, uint8_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) uint32_t *response, u8 *tag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) uint8_t rtag = ioread8(master->sram + STAT_RTAG) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) uint8_t rcrc = ioread8(master->sram + STAT_RCRC) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) uint32_t rdata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) uint32_t crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) uint8_t ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) *tag = ack = rtag & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* we have a whole message now; check CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) crc = crc4(0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) crc = crc4(crc, rtag, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (ack == FSI_RESP_ACK && size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rdata = ioread32be(master->sram + RSP_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) crc = crc4(crc, rdata, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (response)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *response = rdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) crc = crc4(crc, rcrc, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) trace_fsi_master_acf_copro_response(master, rtag, rcrc, rdata, crc == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (crc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Check if it's all 1's or all 0's, that probably means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * the host is off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if ((rtag == 0xf && rcrc == 0xf) || (rtag == 0 && rcrc == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dev_dbg(master->dev, "Bad response CRC !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int send_term(struct fsi_master_acf *master, uint8_t slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct fsi_msg cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) uint8_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) build_term_command(&cmd, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) rc = send_request(master, &cmd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_warn(master->dev, "Error %d sending term\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) rc = read_copro_response(master, 0, NULL, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "TERM failed; lost communication with slave\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) } else if (tag != FSI_RESP_ACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(master->dev, "TERM failed; response %d\n", tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static void dump_ucode_trace(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) char trbuf[52];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_dbg(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "CMDSTAT:%08x RTAG=%02x RCRC=%02x RDATA=%02x #INT=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ioread32be(master->sram + CMD_STAT_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ioread8(master->sram + STAT_RTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ioread8(master->sram + STAT_RCRC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ioread32be(master->sram + RSP_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ioread32be(master->sram + INT_CNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = 0; i < 512; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) uint8_t v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if ((i % 16) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) p = trbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) v = ioread8(master->sram + TRACEBUF + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) p += sprintf(p, "%02x ", v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (((i % 16) == 15) || v == TR_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_dbg(master->dev, "%s\n", trbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (v == TR_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static int handle_response(struct fsi_master_acf *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) uint8_t slave, uint8_t size, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int busy_count = 0, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int crc_err_retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct fsi_msg cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) uint32_t response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) uint8_t tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) rc = read_copro_response(master, size, &response, &tag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Handle retries on CRC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (rc == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Too many retries ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (crc_err_retries++ > FSI_CRC_ERR_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * Pass it up as a -EIO otherwise upper level will retry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * the whole command which isn't what we want here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto bail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) trace_fsi_master_acf_crc_rsp_error(master, crc_err_retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (master->trace_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dump_ucode_trace(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rc = clock_zeros(master, FSI_MASTER_EPOLL_CLOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_warn(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Error %d clocking zeros for E_POLL\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) build_epoll_command(&cmd, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) rc = send_request(master, &cmd, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_warn(master->dev, "Error %d sending E_POLL\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) switch (tag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case FSI_RESP_ACK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (size && data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (size == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *(__be32 *)data = cpu_to_be32(response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) else if (size == 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) *(__be16 *)data = cpu_to_be16(response);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *(u8 *)data = response;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case FSI_RESP_BUSY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Its necessary to clock slave before issuing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * d-poll, not indicated in the hardware protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * spec. < 20 clocks causes slave to hang, 21 ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) dev_dbg(master->dev, "Busy, retrying...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (master->trace_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dump_ucode_trace(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) rc = clock_zeros(master, FSI_MASTER_DPOLL_CLOCKS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev_warn(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "Error %d clocking zeros for D_POLL\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (busy_count++ < FSI_MASTER_MAX_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) build_dpoll_command(&cmd, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) rc = send_request(master, &cmd, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_warn(master->dev, "Error %d sending D_POLL\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_dbg(master->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "ERR slave is stuck in busy state, issuing TERM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) send_term(master, slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case FSI_RESP_ERRA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dev_dbg(master->dev, "ERRA received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (master->trace_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dump_ucode_trace(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case FSI_RESP_ERRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_dbg(master->dev, "ERRC received\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (master->trace_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dump_ucode_trace(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rc = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (busy_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) trace_fsi_master_acf_poll_response_busy(master, busy_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int fsi_master_acf_xfer(struct fsi_master_acf *master, uint8_t slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct fsi_msg *cmd, size_t resp_len, void *resp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int rc = -EAGAIN, retries = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) resp_len <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) while ((retries++) < FSI_CRC_ERR_RETRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) rc = send_request(master, cmd, resp_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (rc != -ESHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dev_warn(master->dev, "Error %d sending command\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) rc = handle_response(master, slave, resp_len, resp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (rc != -EAGAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_dbg(master->dev, "ECRC retry %d\n", retries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Pace it a bit before retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int fsi_master_acf_read(struct fsi_master *_master, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) uint8_t id, uint32_t addr, void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct fsi_msg cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) dev_dbg(master->dev, "read id %d addr %x size %zd\n", id, addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) build_ar_command(master, &cmd, id, addr, size, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rc = fsi_master_acf_xfer(master, id, &cmd, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) last_address_update(master, id, rc == 0, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_dbg(master->dev, "read id %d addr 0x%08x err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) id, addr, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int fsi_master_acf_write(struct fsi_master *_master, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) uint8_t id, uint32_t addr, const void *val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct fsi_msg cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) build_ar_command(master, &cmd, id, addr, size, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_dbg(master->dev, "write id %d addr %x size %zd raw_data: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) id, addr, size, *(uint32_t *)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) last_address_update(master, id, rc == 0, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) dev_dbg(master->dev, "write id %d addr 0x%08x err: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) id, addr, rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int fsi_master_acf_term(struct fsi_master *_master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int link, uint8_t id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct fsi_msg cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) build_term_command(&cmd, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dev_dbg(master->dev, "term id %d\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) rc = fsi_master_acf_xfer(master, id, &cmd, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) last_address_update(master, id, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int fsi_master_acf_break(struct fsi_master *_master, int link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (master->external_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_dbg(master->dev, "sending BREAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) rc = do_copro_command(master, CMD_BREAK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) last_address_update(master, 0, false, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Wait for logic reset to take effect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) udelay(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void reset_cf(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) usleep_range(20,20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) regmap_write(master->scu, SCU_COPRO_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) usleep_range(20,20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void start_cf(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) regmap_write(master->scu, SCU_COPRO_CTRL, SCU_COPRO_CLK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static void setup_ast2500_cf_maps(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * Note about byteswap setting: the bus is wired backwards,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * so setting the byteswap bit actually makes the ColdFire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * work "normally" for a BE processor, ie, put the MSB in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * the lowest address byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * We thus need to set the bit for our main memory which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * contains our program code. We create two mappings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * the register, one with each setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Segments 2 and 3 has a "swapped" mapping (BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * and 6 and 7 have a non-swapped mapping (LE) which allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * us to avoid byteswapping register accesses since the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * registers are all LE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Setup segment 0 to our memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) regmap_write(master->scu, SCU_2500_COPRO_SEG0, master->cf_mem_addr |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) SCU_2500_COPRO_SEG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Segments 2 and 3 to sysregs with byteswap (for SRAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) regmap_write(master->scu, SCU_2500_COPRO_SEG2, SYSREG_BASE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SCU_2500_COPRO_SEG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regmap_write(master->scu, SCU_2500_COPRO_SEG3, SYSREG_BASE | 0x100000 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SCU_2500_COPRO_SEG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* And segment 6 and 7 to sysregs no byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) regmap_write(master->scu, SCU_2500_COPRO_SEG6, SYSREG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) regmap_write(master->scu, SCU_2500_COPRO_SEG7, SYSREG_BASE | 0x100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Memory cachable, regs and SRAM not cachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) regmap_write(master->scu, SCU_2500_COPRO_CACHE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) SCU_2500_COPRO_SEG0_CACHE_EN | SCU_2500_COPRO_CACHE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static void setup_ast2400_cf_maps(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Setup segment 0 to our memory region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) regmap_write(master->scu, SCU_2400_COPRO_SEG0, master->cf_mem_addr |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SCU_2400_COPRO_SEG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Segments 2 to sysregs with byteswap (for SRAM) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) regmap_write(master->scu, SCU_2400_COPRO_SEG2, SYSREG_BASE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) SCU_2400_COPRO_SEG_SWAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* And segment 6 to sysregs no byteswap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) regmap_write(master->scu, SCU_2400_COPRO_SEG6, SYSREG_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Memory cachable, regs and SRAM not cachable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) regmap_write(master->scu, SCU_2400_COPRO_CACHE_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) SCU_2400_COPRO_SEG0_CACHE_EN | SCU_2400_COPRO_CACHE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void setup_common_fw_config(struct fsi_master_acf *master,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) iowrite16be(master->gpio_clk_vreg, base + HDR_CLOCK_GPIO_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) iowrite16be(master->gpio_clk_dreg, base + HDR_CLOCK_GPIO_DADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) iowrite16be(master->gpio_dat_vreg, base + HDR_DATA_GPIO_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) iowrite16be(master->gpio_dat_dreg, base + HDR_DATA_GPIO_DADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) iowrite16be(master->gpio_tra_vreg, base + HDR_TRANS_GPIO_VADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) iowrite16be(master->gpio_tra_dreg, base + HDR_TRANS_GPIO_DADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) iowrite8(master->gpio_clk_bit, base + HDR_CLOCK_GPIO_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) iowrite8(master->gpio_dat_bit, base + HDR_DATA_GPIO_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) iowrite8(master->gpio_tra_bit, base + HDR_TRANS_GPIO_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void setup_ast2500_fw_config(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) void __iomem *base = master->cf_mem + HDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) setup_common_fw_config(master, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) iowrite32be(FW_CONTROL_USE_STOP, base + HDR_FW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void setup_ast2400_fw_config(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) void __iomem *base = master->cf_mem + HDR_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) setup_common_fw_config(master, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) iowrite32be(FW_CONTROL_CONT_CLOCK|FW_CONTROL_DUMMY_RD, base + HDR_FW_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int setup_gpios_for_copro(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* This aren't under ColdFire control, just set them up appropriately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) gpiod_direction_output(master->gpio_mux, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) gpiod_direction_output(master->gpio_enable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* Those are under ColdFire control, let it configure them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) rc = aspeed_gpio_copro_grab_gpio(master->gpio_clk, &master->gpio_clk_vreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) &master->gpio_clk_dreg, &master->gpio_clk_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_err(master->dev, "failed to assign clock gpio to coprocessor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rc = aspeed_gpio_copro_grab_gpio(master->gpio_data, &master->gpio_dat_vreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) &master->gpio_dat_dreg, &master->gpio_dat_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) dev_err(master->dev, "failed to assign data gpio to coprocessor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) aspeed_gpio_copro_release_gpio(master->gpio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) rc = aspeed_gpio_copro_grab_gpio(master->gpio_trans, &master->gpio_tra_vreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) &master->gpio_tra_dreg, &master->gpio_tra_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(master->dev, "failed to assign trans gpio to coprocessor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) aspeed_gpio_copro_release_gpio(master->gpio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) aspeed_gpio_copro_release_gpio(master->gpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static void release_copro_gpios(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) aspeed_gpio_copro_release_gpio(master->gpio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) aspeed_gpio_copro_release_gpio(master->gpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) aspeed_gpio_copro_release_gpio(master->gpio_trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int load_copro_firmware(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint16_t sig = 0, wanted_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) const u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) size_t size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* Get the binary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rc = request_firmware(&fw, FW_FILE_NAME, master->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) master->dev, "Error %d to load firmware '%s' !\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) rc, FW_FILE_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Which image do we want ? (shared vs. split clock/data GPIOs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (master->gpio_clk_vreg == master->gpio_dat_vreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) wanted_sig = SYS_SIG_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) wanted_sig = SYS_SIG_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_dbg(master->dev, "Looking for image sig %04x\n", wanted_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Try to find it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) for (data = fw->data; data < (fw->data + fw->size);) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) sig = be16_to_cpup((__be16 *)(data + HDR_OFFSET + HDR_SYS_SIG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) size = be32_to_cpup((__be32 *)(data + HDR_OFFSET + HDR_FW_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (sig == wanted_sig)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) data += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (sig != wanted_sig) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) dev_err(master->dev, "Failed to locate image sig %04x in FW blob\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) wanted_sig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) goto release_fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (size > master->cf_mem_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(master->dev, "FW size (%zd) bigger than memory reserve (%zd)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) fw->size, master->cf_mem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) memcpy_toio(master->cf_mem, data, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) release_fw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int check_firmware_image(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) uint32_t fw_vers, fw_api, fw_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) fw_vers = ioread16be(master->cf_mem + HDR_OFFSET + HDR_FW_VERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) fw_api = ioread16be(master->cf_mem + HDR_OFFSET + HDR_API_VERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) fw_options = ioread32be(master->cf_mem + HDR_OFFSET + HDR_FW_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) master->trace_enabled = !!(fw_options & FW_OPTION_TRACE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* Check version and signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_info(master->dev, "ColdFire initialized, firmware v%d API v%d.%d (trace %s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) fw_vers, fw_api >> 8, fw_api & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) master->trace_enabled ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if ((fw_api >> 8) != API_VERSION_MAJ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_err(master->dev, "Unsupported coprocessor API version !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int copro_enable_sw_irq(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * Enable coprocessor interrupt input. I've had problems getting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * value to stick, so try in a loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) for (timeout = 0; timeout < 10; timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) iowrite32(0x2, master->cvic + CVIC_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val = ioread32(master->cvic + CVIC_EN_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (val & 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!(val & 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dev_err(master->dev, "Failed to enable coprocessor interrupt !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int fsi_master_acf_setup(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int timeout, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Make sure the ColdFire is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) reset_cf(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * Clear SRAM. This needs to happen before we setup the GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * as we might start trying to arbitrate as soon as that happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) memset_io(master->sram, 0, SRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* Configure GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) rc = setup_gpios_for_copro(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Load the firmware into the reserved memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) rc = load_copro_firmware(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Read signature and check versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) rc = check_firmware_image(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Setup coldfire memory map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (master->is_ast2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) setup_ast2500_cf_maps(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) setup_ast2500_fw_config(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) setup_ast2400_cf_maps(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) setup_ast2400_fw_config(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* Start the ColdFire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) start_cf(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* Wait for status register to indicate command completion
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * which signals the initialization is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (timeout = 0; timeout < 10; timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) val = ioread8(master->sram + CF_STARTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_err(master->dev, "Coprocessor startup timeout !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* Configure echo & send delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Enable SW interrupt to copro if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (master->cvic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) rc = copro_enable_sw_irq(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* An error occurred, don't leave the coprocessor running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) reset_cf(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) /* Release the GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) release_copro_gpios(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static void fsi_master_acf_terminate(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * A GPIO arbitration requestion could come in while this is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * happening. To avoid problems, we disable interrupts so it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * cannot preempt us on this CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Stop the coprocessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) reset_cf(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* We mark the copro not-started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) iowrite32(0, master->sram + CF_STARTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* We mark the ARB register as having given up arbitration to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * deal with a potential race with the arbitration request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) iowrite8(ARB_ARM_ACK, master->sram + ARB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Return the GPIOs to the ARM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) release_copro_gpios(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void fsi_master_acf_setup_external(struct fsi_master_acf *master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* Setup GPIOs for external FSI master (FSP box) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) gpiod_direction_output(master->gpio_mux, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) gpiod_direction_output(master->gpio_trans, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) gpiod_direction_output(master->gpio_enable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) gpiod_direction_input(master->gpio_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) gpiod_direction_input(master->gpio_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static int fsi_master_acf_link_enable(struct fsi_master *_master, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int rc = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (!master->external_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) gpiod_set_value(master->gpio_enable, enable ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static int fsi_master_acf_link_config(struct fsi_master *_master, int link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u8 t_send_delay, u8 t_echo_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct fsi_master_acf *master = to_fsi_master_acf(_master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (link != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) master->t_send_delay = t_send_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) master->t_echo_delay = t_echo_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev_dbg(master->dev, "Changing delays: send=%d echo=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) t_send_delay, t_echo_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) iowrite8(master->t_send_delay, master->sram + SEND_DLY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) iowrite8(master->t_echo_delay, master->sram + ECHO_DLY_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static ssize_t external_mode_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct fsi_master_acf *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return snprintf(buf, PAGE_SIZE - 1, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) master->external_mode ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static ssize_t external_mode_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct device_attribute *attr, const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct fsi_master_acf *master = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bool external_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) err = kstrtoul(buf, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) external_mode = !!val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (external_mode == master->external_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) master->external_mode = external_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (master->external_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fsi_master_acf_terminate(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) fsi_master_acf_setup_external(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) fsi_master_acf_setup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fsi_master_rescan(&master->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static DEVICE_ATTR(external_mode, 0664,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) external_mode_show, external_mode_store);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static int fsi_master_acf_gpio_request(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct fsi_master_acf *master = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) /* Note: This doesn't require holding out mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Write reqest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) iowrite8(ARB_ARM_REQ, master->sram + ARB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) * There is a race (which does happen at boot time) when we get an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * arbitration request as we are either about to or just starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * the coprocessor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * To handle it, we first check if we are running. If not yet we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * check whether the copro is started in the SCU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) * If it's not started, we can basically just assume we have arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * and return. Otherwise, we wait normally expecting for the arbitration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * to eventually complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ioread32(master->sram + CF_STARTED) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) unsigned int reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) regmap_read(master->scu, SCU_COPRO_CTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (!(reg & SCU_COPRO_CLK_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Ring doorbell if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (master->cvic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (timeout = 0; timeout < 10000; timeout++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) val = ioread8(master->sram + ARB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (val != ARB_ARM_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* If it failed, override anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (val != ARB_ARM_ACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) dev_warn(master->dev, "GPIO request arbitration timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static int fsi_master_acf_gpio_release(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct fsi_master_acf *master = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Write release */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) iowrite8(0, master->sram + ARB_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* Ring doorbell if any */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (master->cvic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) iowrite32(0x2, master->cvic + CVIC_TRIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static void fsi_master_acf_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct fsi_master_acf *master = to_fsi_master_acf(dev_to_fsi_master(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* Cleanup, stop coprocessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) fsi_master_acf_terminate(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) aspeed_gpio_copro_set_ops(NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* Free resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) of_node_put(dev_of_node(master->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) kfree(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static const struct aspeed_gpio_copro_ops fsi_master_acf_gpio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .request_access = fsi_master_acf_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .release_access = fsi_master_acf_gpio_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int fsi_master_acf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct device_node *np, *mnode = dev_of_node(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct genpool_data_fixed gpdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct fsi_master_acf *master;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct gpio_desc *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) uint32_t cf_mem_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) master = kzalloc(sizeof(*master), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (!master)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) master->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) master->master.dev.parent = master->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) master->last_addr = LAST_ADDR_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* AST2400 vs. AST2500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) master->is_ast2500 = of_device_is_compatible(mnode, "aspeed,ast2500-cf-fsi-master");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* Grab the SCU, we'll need to access it to configure the coprocessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (master->is_ast2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) master->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2400-scu");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (IS_ERR(master->scu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dev_err(&pdev->dev, "failed to find SCU regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) rc = PTR_ERR(master->scu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Grab all the GPIOs we need */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dev_err(&pdev->dev, "failed to get clock gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) rc = PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) master->gpio_clk = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) gpio = devm_gpiod_get(&pdev->dev, "data", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(&pdev->dev, "failed to get data gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) rc = PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) master->gpio_data = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* Optional GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) dev_err(&pdev->dev, "failed to get trans gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rc = PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) master->gpio_trans = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_err(&pdev->dev, "failed to get enable gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) rc = PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) master->gpio_enable = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (IS_ERR(gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dev_err(&pdev->dev, "failed to get mux gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) rc = PTR_ERR(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) master->gpio_mux = gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Grab the reserved memory region (use DMA API instead ?) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) np = of_parse_phandle(mnode, "memory-region", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(&pdev->dev, "Didn't find reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) rc = of_address_to_resource(np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_err(&pdev->dev, "Couldn't address to resource for reserved memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) master->cf_mem_size = resource_size(&res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) master->cf_mem_addr = (uint32_t)res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) cf_mem_align = master->is_ast2500 ? 0x00100000 : 0x00200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (master->cf_mem_addr & (cf_mem_align - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_err(&pdev->dev, "Reserved memory has insufficient alignment\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) master->cf_mem = devm_ioremap_resource(&pdev->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (IS_ERR(master->cf_mem)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rc = PTR_ERR(master->cf_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dev_err(&pdev->dev, "Error %d mapping coldfire memory\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_dbg(&pdev->dev, "DRAM allocation @%x\n", master->cf_mem_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* AST2500 has a SW interrupt to the coprocessor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (master->is_ast2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) /* Grab the CVIC (ColdFire interrupts controller) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) np = of_parse_phandle(mnode, "aspeed,cvic", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) dev_err(&pdev->dev, "Didn't find CVIC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) master->cvic = devm_of_iomap(&pdev->dev, np, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (IS_ERR(master->cvic)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) rc = PTR_ERR(master->cvic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_err(&pdev->dev, "Error %d mapping CVIC\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) rc = of_property_read_u32(np, "copro-sw-interrupts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &master->cvic_sw_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) dev_err(&pdev->dev, "Can't find coprocessor SW interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) /* Grab the SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) master->sram_pool = of_gen_pool_get(dev_of_node(&pdev->dev), "aspeed,sram", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!master->sram_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_err(&pdev->dev, "Can't find sram pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Current microcode only deals with fixed location in SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) gpdf.offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) master->sram = (void __iomem *)gen_pool_alloc_algo(master->sram_pool, SRAM_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) gen_pool_fixed_alloc, &gpdf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!master->sram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) dev_err(&pdev->dev, "Failed to allocate sram from pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev_dbg(&pdev->dev, "SRAM allocation @%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) (unsigned long)gen_pool_virt_to_phys(master->sram_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) (unsigned long)master->sram));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * Hookup with the GPIO driver for arbitration of GPIO banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) * ownership.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) aspeed_gpio_copro_set_ops(&fsi_master_acf_gpio_ops, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) /* Default FSI command delays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) master->t_send_delay = FSI_SEND_DELAY_CLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) master->t_echo_delay = FSI_ECHO_DELAY_CLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) master->master.n_links = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (master->is_ast2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) master->master.read = fsi_master_acf_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) master->master.write = fsi_master_acf_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) master->master.term = fsi_master_acf_term;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) master->master.send_break = fsi_master_acf_break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) master->master.link_enable = fsi_master_acf_link_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) master->master.link_config = fsi_master_acf_link_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) master->master.dev.of_node = of_node_get(dev_of_node(master->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) master->master.dev.release = fsi_master_acf_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) platform_set_drvdata(pdev, master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) mutex_init(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) mutex_lock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) rc = fsi_master_acf_setup(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mutex_unlock(&master->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) goto release_of_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) rc = device_create_file(&pdev->dev, &dev_attr_external_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) goto stop_copro;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) rc = fsi_master_register(&master->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) if (!rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) device_remove_file(master->dev, &dev_attr_external_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) put_device(&master->master.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) stop_copro:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) fsi_master_acf_terminate(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) release_of_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) aspeed_gpio_copro_set_ops(NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) gen_pool_free(master->sram_pool, (unsigned long)master->sram, SRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) of_node_put(dev_of_node(master->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) kfree(master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static int fsi_master_acf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct fsi_master_acf *master = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) device_remove_file(master->dev, &dev_attr_external_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) fsi_master_unregister(&master->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static const struct of_device_id fsi_master_acf_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) { .compatible = "aspeed,ast2400-cf-fsi-master" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) { .compatible = "aspeed,ast2500-cf-fsi-master" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) MODULE_DEVICE_TABLE(of, fsi_master_acf_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static struct platform_driver fsi_master_acf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .name = "fsi-master-acf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .of_match_table = fsi_master_acf_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .probe = fsi_master_acf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .remove = fsi_master_acf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) module_platform_driver(fsi_master_acf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags