^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __CF_FSI_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __CF_FSI_FW_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * uCode file layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 0000...03ff : m68k exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 0400...04ff : Header info & boot config block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 0500....... : Code & stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Header info & boot config area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * The Header info is built into the ucode and provide version and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * platform information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * the Boot config needs to be adjusted by the ARM prior to starting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * the ucode if the Command/Status area isn't at 0x320000 in CF space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * (ie. beginning of SRAM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HDR_OFFSET 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Info: Signature & version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HDR_SYS_SIG 0x00 /* 2 bytes system signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SYS_SIG_SHARED 0x5348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SYS_SIG_SPLIT 0x5350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define API_VERSION_MAJ 2 /* Current version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define API_VERSION_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Boot Config: Address of Command/Status area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Command/Status area layout: Main part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Command/Status register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * +---------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * | STAT | RLEN | CLEN | CMD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * | 8 | 8 | 8 | 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * +---------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * status | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Response len | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * (in bits) | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * Command len |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * (in bits) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Command code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Due to the big endian layout, that means that a byte read will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * return the status byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CMD_STAT_REG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CMD_REG_CMD_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMD_REG_CMD_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMD_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMD_COMMAND 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMD_BREAK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMD_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CMD_REG_CLEN_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMD_REG_CLEN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMD_REG_RLEN_MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMD_REG_RLEN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMD_REG_STAT_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMD_REG_STAT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STAT_WORKING 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STAT_COMPLETE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STAT_ERR_INVAL_CMD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STAT_ERR_INVAL_IRQ 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STAT_ERR_MTOE 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Response tag & CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STAT_RTAG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Response CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STAT_RCRC 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Echo and Send delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ECHO_DLY_REG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SEND_DLY_REG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Command data area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Last byte of message must be left aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMD_DATA 0x10 /* 64 bit of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Response data area, right aligned, unused top bits are 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RSP_DATA 0x20 /* 32 bit of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define INT_CNT 0x30 /* 32-bit interrupt count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CF_STARTED 0x38 /* byte, set to -1 when copro started */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * SRAM layout: GPIO arbitration part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ARB_REG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ARB_ARM_REQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ARB_ARM_ACK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Misc2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CF_RESET_D0 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CF_RESET_D1 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BAD_INT_S0 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BAD_INT_S1 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define STOP_CNT 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Internal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * SRAM layout: Trace buffer (debug builds only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TRACEBUF 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TR_CLKOBIT0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TR_CLKOBIT1 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TR_CLKOSTART 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TR_OLEN 0x83 /* + len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TR_CLKZ 0x84 /* + count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TR_CLKWSTART 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TR_CLKTAG 0x86 /* + tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TR_CLKDATA 0x87 /* + len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TR_CLKCRC 0x88 /* + raw crc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TR_CLKIBIT0 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TR_CLKIBIT1 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TR_END 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #endif /* __CF_FSI_FW_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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