^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2011-2015 Xilinx Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015, National Instruments Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * in their vendor tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Offsets into SLCR regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* FPGA Software Reset Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLCR_FPGA_RST_CTRL_OFFSET 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Level Shifters Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLCR_LVL_SHFTR_EN_OFFSET 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Constant Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CTRL_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Lock Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LOCK_OFFSET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define INT_STS_OFFSET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define INT_MASK_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define STATUS_OFFSET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* DMA Source Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMA_SRC_ADDR_OFFSET 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* DMA Destination Address Reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMA_DST_ADDR_OFFSET 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* DMA Source Transfer Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DMA_SRC_LEN_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* DMA Destination Transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMA_DEST_LEN_OFFSET 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Unlock Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define UNLOCK_OFFSET 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Misc. Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MCTRL_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Control Register Bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Signal to reset FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CTRL_PCFG_PROG_B_MASK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Enable PCAP for PR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CTRL_PCAP_PR_MASK BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Enable PCAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CTRL_PCAP_MODE_MASK BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Lower rate to allow decrypt on the fly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CTRL_PCAP_RATE_EN_MASK BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* System booted in secure mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTRL_SEC_EN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Miscellaneous Control Register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Internal PCAP loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MCTRL_PCAP_LPBK_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Status register bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* FPGA init status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STATUS_DMA_Q_F BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STATUS_DMA_Q_E BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STATUS_PCFG_INIT_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Interrupt Status/Mask Register Bit definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* DMA command done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IXR_DMA_DONE_MASK BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* DMA and PCAP cmd done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IXR_D_P_DONE_MASK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* FPGA programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IXR_PCFG_DONE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IXR_ERROR_FLAGS_MASK 0x00F0C860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IXR_ALL_MASK 0xF8F7F87F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Miscellaneous constant values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Invalid DMA addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DMA_INVALID_ADDRESS GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Used to unlock the dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UNLOCK_MASK 0x757bdf0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Timeout for polling reset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define INIT_POLL_TIMEOUT 2500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Delay for polling reset bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define INIT_POLL_DELAY 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Signal this is the last DMA transfer, wait for the AXI and PCAP before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * interrupting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DMA_SRC_LAST_TRANSFER 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Timeout for DMA completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMA_TIMEOUT_MS 5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Masks for controlling stuff in SLCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Disable all Level shifters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LVL_SHFTR_DISABLE_ALL_MASK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Enable Level shifters from PS to PL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LVL_SHFTR_ENABLE_PS_TO_PL 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Enable Level shifters from PL to PS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LVL_SHFTR_ENABLE_PL_TO_PS 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Enable global resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define FPGA_RST_ALL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Disable global resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FPGA_RST_NONE_MASK 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct zynq_fpga_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct regmap *slcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) spinlock_t dma_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int dma_elm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int dma_nelms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct scatterlist *cur_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct completion dma_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static inline void zynq_fpga_write(struct zynq_fpga_priv *priv, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) writel(val, priv->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static inline u32 zynq_fpga_read(const struct zynq_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return readl(priv->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define zynq_fpga_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) timeout_us)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Cause the specified irq mask bits to generate IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void zynq_fpga_set_irq(struct zynq_fpga_priv *priv, u32 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) zynq_fpga_write(priv, INT_MASK_OFFSET, ~enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Must be called with dma_lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void zynq_step_dma(struct zynq_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) first = priv->dma_elm == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) while (priv->cur_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* Feed the DMA queue until it is full. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (zynq_fpga_read(priv, STATUS_OFFSET) & STATUS_DMA_Q_F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) addr = sg_dma_address(priv->cur_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) len = sg_dma_len(priv->cur_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (priv->dma_elm + 1 == priv->dma_nelms) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* The last transfer waits for the PCAP to finish too,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * notice this also changes the irq_mask to ignore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * IXR_DMA_DONE_MASK which ensures we do not trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * the completion too early.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) addr |= DMA_SRC_LAST_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) priv->cur_sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv->cur_sg = sg_next(priv->cur_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv->dma_elm++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) zynq_fpga_write(priv, DMA_SRC_ADDR_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) zynq_fpga_write(priv, DMA_DST_ADDR_OFFSET, DMA_INVALID_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) zynq_fpga_write(priv, DMA_SRC_LEN_OFFSET, len / 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) zynq_fpga_write(priv, DMA_DEST_LEN_OFFSET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Once the first transfer is queued we can turn on the ISR, future
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * calls to zynq_step_dma will happen from the ISR context. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * dma_lock spinlock guarentees this handover is done coherently, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * ISR enable is put at the end to avoid another CPU spinning in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * ISR on this lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (first && priv->cur_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) zynq_fpga_set_irq(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IXR_DMA_DONE_MASK | IXR_ERROR_FLAGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) } else if (!priv->cur_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* The last transfer changes to DMA & PCAP mode since we do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * not want to continue until everything has been flushed into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * the PCAP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) zynq_fpga_set_irq(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IXR_D_P_DONE_MASK | IXR_ERROR_FLAGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static irqreturn_t zynq_fpga_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct zynq_fpga_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* If anything other than DMA completion is reported stop and hand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * control back to zynq_fpga_ops_write, something went wrong,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * otherwise progress the DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_lock(&priv->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (!(intr_status & IXR_ERROR_FLAGS_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (intr_status & IXR_DMA_DONE_MASK) && priv->cur_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) zynq_fpga_write(priv, INT_STS_OFFSET, IXR_DMA_DONE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) zynq_step_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) spin_unlock(&priv->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_unlock(&priv->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) zynq_fpga_set_irq(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) complete(&priv->dma_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Sanity check the proposed bitstream. It must start with the sync word in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * the correct byte order, and be dword aligned. The input is a Xilinx .bin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * file with every 32 bit quantity swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (; count >= 4; buf += 4, count -= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) buf[3] == 0xaa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int zynq_fpga_ops_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct zynq_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 ctrl, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* check if bitstream is encrypted & and system's still secure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (!(ctrl & CTRL_SEC_EN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "System not secure, can't use crypted bitstreams\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* don't globally reset PL if we're doing partial reconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!zynq_fpga_has_sync(buf, count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "Invalid bitstream, could not find a sync word. Bitstream must be a byte swapped .bin file\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* assert AXI interface resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FPGA_RST_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* disable all level shifters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LVL_SHFTR_DISABLE_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* enable level shifters from PS to PL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) LVL_SHFTR_ENABLE_PS_TO_PL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* create a rising edge on PCFG_INIT. PCFG_INIT follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * PCFG_PROG_B, so we need to poll it after setting PCFG_PROG_B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * to make sure the rising edge actually happens.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Note: PCFG_PROG_B is low active, sequence as described in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * UG585 v1.10 page 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ctrl |= CTRL_PCFG_PROG_B_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) status & STATUS_PCFG_INIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) INIT_POLL_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) INIT_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctrl &= ~CTRL_PCFG_PROG_B_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) !(status & STATUS_PCFG_INIT_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) INIT_POLL_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) INIT_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(&mgr->dev, "Timeout waiting for !PCFG_INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ctrl |= CTRL_PCFG_PROG_B_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) zynq_fpga_write(priv, CTRL_OFFSET, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) err = zynq_fpga_poll_timeout(priv, STATUS_OFFSET, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) status & STATUS_PCFG_INIT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) INIT_POLL_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) INIT_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(&mgr->dev, "Timeout waiting for PCFG_INIT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* set configuration register with following options:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * - enable PCAP interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * - set throughput for maximum speed (if bistream not crypted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * - set CPU in user mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ctrl = zynq_fpga_read(priv, CTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (info->flags & FPGA_MGR_ENCRYPTED_BITSTREAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) zynq_fpga_write(priv, CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) | CTRL_PCAP_RATE_EN_MASK | ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) zynq_fpga_write(priv, CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (CTRL_PCAP_PR_MASK | CTRL_PCAP_MODE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) | ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* We expect that the command queue is empty right now. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status = zynq_fpga_read(priv, STATUS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((status & STATUS_DMA_Q_F) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) (status & STATUS_DMA_Q_E) != STATUS_DMA_Q_E) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_err(&mgr->dev, "DMA command queue not right\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* ensure internal PCAP loopback is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ctrl = zynq_fpga_read(priv, MCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) zynq_fpga_write(priv, MCTRL_OFFSET, (~MCTRL_PCAP_LPBK_MASK & ctrl));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int zynq_fpga_ops_write(struct fpga_manager *mgr, struct sg_table *sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct zynq_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const char *why;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* The hardware can only DMA multiples of 4 bytes, and it requires the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * starting addresses to be aligned to 64 bits (UG585 pg 212).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) for_each_sg(sgt->sgl, sg, sgt->nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if ((sg->offset % 8) || (sg->length % 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "Invalid bitstream, chunks must be aligned\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv->dma_nelms =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dma_map_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (priv->dma_nelms == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(&mgr->dev, "Unable to DMA map (TO_DEVICE)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reinit_completion(&priv->dma_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* zynq_step_dma will turn on interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) spin_lock_irqsave(&priv->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) priv->dma_elm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) priv->cur_sg = sgt->sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) zynq_step_dma(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) spin_unlock_irqrestore(&priv->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) timeout = wait_for_completion_timeout(&priv->dma_done,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msecs_to_jiffies(DMA_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_lock_irqsave(&priv->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) zynq_fpga_set_irq(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) priv->cur_sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spin_unlock_irqrestore(&priv->dma_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* There doesn't seem to be a way to force cancel any DMA, so if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * something went wrong we are relying on the hardware to have halted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * the DMA before we get here, if there was we could use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * wait_for_completion_interruptible too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (intr_status & IXR_ERROR_FLAGS_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) why = "DMA reported error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto out_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (priv->cur_sg ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) !((intr_status & IXR_D_P_DONE_MASK) == IXR_D_P_DONE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) why = "DMA timed out";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) why = "DMA did not complete";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) err = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) goto out_report;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) goto out_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) out_report:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "%s: INT_STS:0x%x CTRL:0x%x LOCK:0x%x INT_MASK:0x%x STATUS:0x%x MCTRL:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) why,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) intr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) zynq_fpga_read(priv, CTRL_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) zynq_fpga_read(priv, LOCK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) zynq_fpga_read(priv, INT_MASK_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) zynq_fpga_read(priv, STATUS_OFFSET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) zynq_fpga_read(priv, MCTRL_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) out_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dma_unmap_sg(mgr->dev.parent, sgt->sgl, sgt->nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct zynq_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Release 'PR' control back to the ICAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) zynq_fpga_write(priv, CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) intr_status & IXR_PCFG_DONE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) INIT_POLL_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) INIT_POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* for the partial reconfig case we didn't touch the level shifters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* enable level shifters from PL to PS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) regmap_write(priv->slcr, SLCR_LVL_SHFTR_EN_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) LVL_SHFTR_ENABLE_PL_TO_PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* deassert AXI interface resets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regmap_write(priv->slcr, SLCR_FPGA_RST_CTRL_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) FPGA_RST_NONE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static enum fpga_mgr_states zynq_fpga_ops_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) u32 intr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct zynq_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) intr_status = zynq_fpga_read(priv, INT_STS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (intr_status & IXR_PCFG_DONE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return FPGA_MGR_STATE_OPERATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct fpga_manager_ops zynq_fpga_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .initial_header_size = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .state = zynq_fpga_ops_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .write_init = zynq_fpga_ops_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .write_sg = zynq_fpga_ops_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .write_complete = zynq_fpga_ops_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int zynq_fpga_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct zynq_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) spin_lock_init(&priv->dma_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) priv->io_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (IS_ERR(priv->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return PTR_ERR(priv->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) priv->slcr = syscon_regmap_lookup_by_phandle(dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (IS_ERR(priv->slcr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_err(dev, "unable to get zynq-slcr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return PTR_ERR(priv->slcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) init_completion(&priv->dma_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (priv->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) priv->clk = devm_clk_get(dev, "ref_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dev_err(dev, "input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* unlock the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) zynq_fpga_write(priv, UNLOCK_OFFSET, UNLOCK_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) zynq_fpga_set_irq(priv, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) zynq_fpga_write(priv, INT_STS_OFFSET, IXR_ALL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) err = devm_request_irq(dev, priv->irq, zynq_fpga_isr, 0, dev_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_err(dev, "unable to request IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mgr = devm_fpga_mgr_create(dev, "Xilinx Zynq FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) &zynq_fpga_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) platform_set_drvdata(pdev, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) err = fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) dev_err(dev, "unable to register FPGA manager\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) clk_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int zynq_fpga_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct zynq_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mgr = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) clk_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct of_device_id zynq_fpga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { .compatible = "xlnx,zynq-devcfg-1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_DEVICE_TABLE(of, zynq_fpga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static struct platform_driver zynq_fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .probe = zynq_fpga_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .remove = zynq_fpga_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .name = "zynq_fpga_manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .of_match_table = of_match_ptr(zynq_fpga_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) module_platform_driver(zynq_fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) MODULE_AUTHOR("Moritz Fischer <moritz.fischer@ettus.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MODULE_DESCRIPTION("Xilinx Zynq FPGA Manager");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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