^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx Spartan6 and 7 Series Slave Serial SPI Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 DENX Software Engineering
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Anatolij Gustschin <agust@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Manage Xilinx FPGA firmware that is loaded over SPI using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * the slave serial configuration interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct xilinx_spi_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct gpio_desc *prog_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct gpio_desc *init_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct gpio_desc *done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int get_done_gpio(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct xilinx_spi_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ret = gpiod_get_value(conf->done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dev_err(&mgr->dev, "Error reading DONE (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static enum fpga_mgr_states xilinx_spi_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (!get_done_gpio(mgr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return FPGA_MGR_STATE_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * wait_for_init_b - wait for the INIT_B pin to have a given state, or wait
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * a given delay if the pin is unavailable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @mgr: The FPGA manager object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @value: Value INIT_B to wait for (1 = asserted = low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @alt_udelay: Delay to wait if the INIT_B GPIO is not available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Returns 0 when the INIT_B GPIO reached the given state or -ETIMEDOUT if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * too much time passed waiting for that. If no INIT_B GPIO is available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * then always return 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int wait_for_init_b(struct fpga_manager *mgr, int value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long alt_udelay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct xilinx_spi_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long timeout = jiffies + msecs_to_jiffies(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if (conf->init_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int ret = gpiod_get_value(conf->init_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (ret == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) usleep_range(100, 400);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) value ? "assert" : "deassert");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) udelay(alt_udelay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int xilinx_spi_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct xilinx_spi_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) gpiod_set_value(conf->prog_b, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gpiod_set_value(conf->prog_b, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gpiod_set_value(conf->prog_b, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) err = wait_for_init_b(mgr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (get_done_gpio(mgr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* program latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) usleep_range(7500, 7600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int xilinx_spi_write(struct fpga_manager *mgr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct xilinx_spi_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *fw_data = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *fw_data_end = fw_data + count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) while (fw_data < fw_data_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) size_t remaining, stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) remaining = fw_data_end - fw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) stride = min_t(size_t, remaining, SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) ret = spi_write(conf->spi, fw_data, stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(&mgr->dev, "SPI error in firmware write: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) fw_data += stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int xilinx_spi_apply_cclk_cycles(struct xilinx_spi_conf *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct spi_device *spi = conf->spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const u8 din_data[1] = { 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = spi_write(conf->spi, din_data, sizeof(din_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(&spi->dev, "applying CCLK cycles failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int xilinx_spi_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct xilinx_spi_conf *conf = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool expired = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * This loop is carefully written such that if the driver is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * scheduled out for more than 'timeout', we still check for DONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * before giving up and we apply 8 extra CCLK cycles in all cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) while (!expired) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) expired = time_after(jiffies, timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) done = get_done_gpio(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (done < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ret = xilinx_spi_apply_cclk_cycles(conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (conf->init_b) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = gpiod_get_value(conf->init_b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_err(&mgr->dev, "Error reading INIT_B (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret ? "CRC error or invalid device\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) : "Missing sync word or incomplete bitstream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dev_err(&mgr->dev, "Timeout after config data transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct fpga_manager_ops xilinx_spi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .state = xilinx_spi_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .write_init = xilinx_spi_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .write = xilinx_spi_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .write_complete = xilinx_spi_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int xilinx_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct xilinx_spi_conf *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (!conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) conf->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* PROGRAM_B is active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (IS_ERR(conf->prog_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return dev_err_probe(&spi->dev, PTR_ERR(conf->prog_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "Failed to get PROGRAM_B gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (IS_ERR(conf->init_b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return dev_err_probe(&spi->dev, PTR_ERR(conf->init_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "Failed to get INIT_B gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (IS_ERR(conf->done))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return dev_err_probe(&spi->dev, PTR_ERR(conf->done),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "Failed to get DONE gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mgr = devm_fpga_mgr_create(&spi->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "Xilinx Slave Serial FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) &xilinx_spi_ops, conf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spi_set_drvdata(spi, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int xilinx_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct fpga_manager *mgr = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const struct of_device_id xlnx_spi_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .compatible = "xlnx,fpga-slave-serial", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) MODULE_DEVICE_TABLE(of, xlnx_spi_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct spi_driver xilinx_slave_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "xlnx-slave-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .of_match_table = of_match_ptr(xlnx_spi_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .probe = xilinx_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .remove = xilinx_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) module_spi_driver(xilinx_slave_spi_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MODULE_DESCRIPTION("Load Xilinx FPGA firmware over SPI");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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