^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2017, National Instruments Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2017, Xilix Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Decoupler IP Core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/fpga/fpga-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CTRL_CMD_DECOUPLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CTRL_CMD_COUPLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CTRL_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct xlnx_pr_decoupler_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 offset, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) writel(val, d->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return readl(d->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct xlnx_pr_decoupler_data *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const struct xlnx_pr_decoupler_data *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) err = clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) status = readl(priv->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return !status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .enable_set = xlnx_pr_decoupler_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .enable_show = xlnx_pr_decoupler_enable_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { .compatible = "xlnx,pr-decoupler-1.00", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { .compatible = "xlnx,pr-decoupler", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct xlnx_pr_decoupler_data *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct fpga_bridge *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) priv->io_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (IS_ERR(priv->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return PTR_ERR(priv->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) priv->clk = devm_clk_get(&pdev->dev, "aclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) dev_err(&pdev->dev, "input clock not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) err = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) dev_err(&pdev->dev, "unable to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &xlnx_pr_decoupler_br_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!br) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) platform_set_drvdata(pdev, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) err = fpga_bridge_register(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct fpga_bridge *bridge = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct xlnx_pr_decoupler_data *p = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fpga_bridge_unregister(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) clk_unprepare(p->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct platform_driver xlnx_pr_decoupler_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .probe = xlnx_pr_decoupler_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .remove = xlnx_pr_decoupler_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "xlnx_pr_decoupler",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module_platform_driver(xlnx_pr_decoupler_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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