^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Technologic Systems TS-73xx SBC FPGA loader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * TS-7300, heavily based on load_fpga.c in their vendor tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TS73XX_FPGA_DATA_REG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TS73XX_FPGA_CONFIG_REG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TS73XX_FPGA_WRITE_DONE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TS73XX_FPGA_WRITE_DONE_TIMEOUT 1000 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TS73XX_FPGA_RESET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TS73XX_FPGA_RESET_LOW_DELAY 30 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TS73XX_FPGA_RESET_HIGH_DELAY 80 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TS73XX_FPGA_LOAD_OK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TS73XX_FPGA_CONFIG_LOAD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct ts73xx_fpga_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static enum fpga_mgr_states ts73xx_fpga_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int ts73xx_fpga_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ts73xx_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Reset the FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) udelay(TS73XX_FPGA_RESET_LOW_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) writeb(TS73XX_FPGA_RESET, priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) udelay(TS73XX_FPGA_RESET_HIGH_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int ts73xx_fpga_write(struct fpga_manager *mgr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ts73xx_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) size_t i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret = readb_poll_timeout(priv->io_base + TS73XX_FPGA_CONFIG_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) reg, !(reg & TS73XX_FPGA_WRITE_DONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1, TS73XX_FPGA_WRITE_DONE_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int ts73xx_fpga_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct ts73xx_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) reg |= TS73XX_FPGA_CONFIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) reg &= ~TS73XX_FPGA_CONFIG_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if ((reg & TS73XX_FPGA_LOAD_OK) != TS73XX_FPGA_LOAD_OK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const struct fpga_manager_ops ts73xx_fpga_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .state = ts73xx_fpga_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .write_init = ts73xx_fpga_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .write = ts73xx_fpga_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .write_complete = ts73xx_fpga_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int ts73xx_fpga_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *kdev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ts73xx_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) priv = devm_kzalloc(kdev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) priv->dev = kdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) priv->io_base = devm_ioremap_resource(kdev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (IS_ERR(priv->io_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return PTR_ERR(priv->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) mgr = devm_fpga_mgr_create(kdev, "TS-73xx FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &ts73xx_fpga_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) platform_set_drvdata(pdev, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int ts73xx_fpga_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct fpga_manager *mgr = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct platform_driver ts73xx_fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "ts73xx-fpga-mgr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .probe = ts73xx_fpga_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .remove = ts73xx_fpga_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) module_platform_driver(ts73xx_fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MODULE_DESCRIPTION("TS-73xx FPGA Manager driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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