^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA Manager Driver for Altera SOCFPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2015 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SOCFPGA_FPGMGR_STAT_OFST 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SOCFPGA_FPGMGR_CTL_OFST 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SOCFPGA_FPGMGR_DCLKCNT_OFST 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SOCFPGA_FPGMGR_DCLKSTAT_OFST 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SOCFPGA_FPGMGR_GPIO_INTEN_OFST 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SOCFPGA_FPGMGR_GPIO_INTMSK_OFST 0x834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST 0x838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SOCFPGA_FPGMGR_GPIO_INT_POL_OFST 0x83c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SOCFPGA_FPGMGR_GPIO_RAW_INTSTAT_OFST 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST 0x850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Register bit defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* SOCFPGA_FPGMGR_STAT register mode field values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SOCFPGA_FPGMGR_STAT_POWER_UP 0x0 /*ramping*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SOCFPGA_FPGMGR_STAT_RESET 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SOCFPGA_FPGMGR_STAT_CFG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SOCFPGA_FPGMGR_STAT_INIT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SOCFPGA_FPGMGR_STAT_USER_MODE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SOCFPGA_FPGMGR_STAT_UNKNOWN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SOCFPGA_FPGMGR_STAT_STATE_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* This is a flag value that doesn't really happen in this register field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SOCFPGA_FPGMGR_STAT_POWER_OFF 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MSEL_PP16_FAST_NOAES_NODC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MSEL_PP16_FAST_AES_NODC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MSEL_PP16_FAST_AESOPT_DC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MSEL_PP16_SLOW_NOAES_NODC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MSEL_PP16_SLOW_AES_NODC 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MSEL_PP16_SLOW_AESOPT_DC 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MSEL_PP32_FAST_NOAES_NODC 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MSEL_PP32_FAST_AES_NODC 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MSEL_PP32_FAST_AESOPT_DC 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MSEL_PP32_SLOW_NOAES_NODC 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MSEL_PP32_SLOW_AES_NODC 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MSEL_PP32_SLOW_AESOPT_DC 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SOCFPGA_FPGMGR_STAT_MSEL_MASK 0x000000f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SOCFPGA_FPGMGR_STAT_MSEL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* SOCFPGA_FPGMGR_CTL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SOCFPGA_FPGMGR_CTL_EN 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SOCFPGA_FPGMGR_CTL_NCE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SOCFPGA_FPGMGR_CTL_NCFGPULL 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CDRATIO_X1 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CDRATIO_X2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CDRATIO_X4 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CDRATIO_X8 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SOCFPGA_FPGMGR_CTL_CDRATIO_MASK 0x000000c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SOCFPGA_FPGMGR_CTL_AXICFGEN 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CFGWDTH_16 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CFGWDTH_32 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* SOCFPGA_FPGMGR_DCLKSTAT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* SOCFPGA_FPGMGR_GPIO_* registers share the same bit positions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SOCFPGA_FPGMGR_MON_NSTATUS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SOCFPGA_FPGMGR_MON_CONF_DONE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SOCFPGA_FPGMGR_MON_INIT_DONE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SOCFPGA_FPGMGR_MON_CRC_ERROR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SOCFPGA_FPGMGR_MON_CVP_CONF_DONE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SOCFPGA_FPGMGR_MON_PR_READY 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SOCFPGA_FPGMGR_MON_PR_ERROR 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SOCFPGA_FPGMGR_MON_PR_DONE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SOCFPGA_FPGMGR_MON_NCONFIG_PIN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SOCFPGA_FPGMGR_MON_NSTATUS_PIN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SOCFPGA_FPGMGR_MON_CONF_DONE_PIN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SOCFPGA_FPGMGR_MON_FPGA_POWER_ON 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SOCFPGA_FPGMGR_MON_STATUS_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SOCFPGA_FPGMGR_NUM_SUPPLIES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SOCFPGA_RESUME_TIMEOUT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* In power-up order. Reverse for power-down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const char *supply_names[SOCFPGA_FPGMGR_NUM_SUPPLIES] __maybe_unused = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "FPGA-1.5V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) "FPGA-1.1V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "FPGA-2.5V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct socfpga_fpga_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) void __iomem *fpga_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void __iomem *fpga_data_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct completion status_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct cfgmgr_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Values to set in the CTRL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* flag that this table entry is a valid mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* For SOCFPGA_FPGMGR_STAT_MSEL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct cfgmgr_mode cfgmgr_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [MSEL_PP16_FAST_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [MSEL_PP16_FAST_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [MSEL_PP16_FAST_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [MSEL_PP16_SLOW_NOAES_NODC] = { CFGWDTH_16 | CDRATIO_X1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [MSEL_PP16_SLOW_AES_NODC] = { CFGWDTH_16 | CDRATIO_X2, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [MSEL_PP16_SLOW_AESOPT_DC] = { CFGWDTH_16 | CDRATIO_X4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [MSEL_PP32_FAST_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [MSEL_PP32_FAST_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [MSEL_PP32_FAST_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [MSEL_PP32_SLOW_NOAES_NODC] = { CFGWDTH_32 | CDRATIO_X1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [MSEL_PP32_SLOW_AES_NODC] = { CFGWDTH_32 | CDRATIO_X4, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [MSEL_PP32_SLOW_AESOPT_DC] = { CFGWDTH_32 | CDRATIO_X8, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static u32 socfpga_fpga_readl(struct socfpga_fpga_priv *priv, u32 reg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return readl(priv->fpga_base_addr + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static void socfpga_fpga_writel(struct socfpga_fpga_priv *priv, u32 reg_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(value, priv->fpga_base_addr + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static u32 socfpga_fpga_raw_readl(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 reg_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return __raw_readl(priv->fpga_base_addr + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void socfpga_fpga_raw_writel(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 reg_offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) __raw_writel(value, priv->fpga_base_addr + reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void socfpga_fpga_data_writel(struct socfpga_fpga_priv *priv, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(value, priv->fpga_data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline void socfpga_fpga_set_bitsl(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val = socfpga_fpga_readl(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) socfpga_fpga_writel(priv, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void socfpga_fpga_clr_bitsl(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 offset, u32 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) val = socfpga_fpga_readl(priv, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val &= ~bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) socfpga_fpga_writel(priv, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static u32 socfpga_fpga_mon_status_get(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SOCFPGA_FPGMGR_MON_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static u32 socfpga_fpga_state_get(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 status = socfpga_fpga_mon_status_get(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if ((status & SOCFPGA_FPGMGR_MON_FPGA_POWER_ON) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return SOCFPGA_FPGMGR_STAT_POWER_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SOCFPGA_FPGMGR_STAT_STATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void socfpga_fpga_clear_done_status(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Set the DCLKCNT, wait for DCLKSTAT to report the count completed, and clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * the complete status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int socfpga_fpga_dclk_set_and_wait_clear(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Clear any existing DONE status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) socfpga_fpga_clear_done_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Issue the DCLK count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_DCLKCNT_OFST, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Poll DCLKSTAT to see if it completed in the timeout period. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) done = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_DCLKSTAT_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (done == SOCFPGA_FPGMGR_DCLKSTAT_DCNTDONE_E_DONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) socfpga_fpga_clear_done_status(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int socfpga_fpga_wait_for_state(struct socfpga_fpga_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int timeout = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * HW doesn't support an interrupt for changes in state, so poll to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * if it matches the requested state within the timeout period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if ((socfpga_fpga_state_get(priv) & state) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) } while (timeout--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void socfpga_fpga_enable_irqs(struct socfpga_fpga_priv *priv, u32 irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* set irqs to level sensitive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTTYPE_LEVEL_OFST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* set interrupt polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INT_POL_OFST, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* clear irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* unmask interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTMSK_OFST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void socfpga_fpga_disable_irqs(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static irqreturn_t socfpga_fpga_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct socfpga_fpga_priv *priv = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 irqs, st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bool conf_done, nstatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* clear irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) irqs = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_INTSTAT_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) socfpga_fpga_raw_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST, irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) st = socfpga_fpga_raw_readl(priv, SOCFPGA_FPGMGR_GPIO_EXT_PORTA_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) conf_done = (st & SOCFPGA_FPGMGR_MON_CONF_DONE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) nstatus = (st & SOCFPGA_FPGMGR_MON_NSTATUS) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* success */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (conf_done && nstatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* disable irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) socfpga_fpga_raw_writel(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SOCFPGA_FPGMGR_GPIO_INTEN_OFST, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) complete(&priv->status_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int socfpga_fpga_wait_for_config_done(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int timeout, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) socfpga_fpga_disable_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) init_completion(&priv->status_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) socfpga_fpga_enable_irqs(priv, SOCFPGA_FPGMGR_MON_CONF_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) timeout = wait_for_completion_interruptible_timeout(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) &priv->status_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) msecs_to_jiffies(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (timeout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) socfpga_fpga_disable_irqs(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int socfpga_fpga_cfg_mode_get(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 msel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) msel = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_STAT_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) msel &= SOCFPGA_FPGMGR_STAT_MSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) msel >>= SOCFPGA_FPGMGR_STAT_MSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Check that this MSEL setting is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if ((msel >= ARRAY_SIZE(cfgmgr_modes)) || !cfgmgr_modes[msel].valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return msel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int socfpga_fpga_cfg_mode_set(struct socfpga_fpga_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* get value from MSEL pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) mode = socfpga_fpga_cfg_mode_get(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (mode < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Adjust CTRL for the CDRATIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ctrl_reg |= cfgmgr_modes[mode].ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Set NCE to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int socfpga_fpga_reset(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct socfpga_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 ctrl_reg, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Step 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * - Set CTRL.CFGWDTH, CTRL.CDRATIO to match cfg mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * - Set CTRL.NCE to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = socfpga_fpga_cfg_mode_set(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Step 2: Set CTRL.EN to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SOCFPGA_FPGMGR_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Step 3: Set CTRL.NCONFIGPULL to 1 to put FPGA in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Step 4: Wait for STATUS.MODE to report FPGA is in reset phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) status = socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Step 5: Set CONTROL.NCONFIGPULL to 0 to release FPGA from reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCFGPULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Timeout waiting for reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * Prepare the FPGA to receive the configuration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct socfpga_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(&mgr->dev, "Partial reconfiguration not supported.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Steps 1 - 5: Reset the FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = socfpga_fpga_reset(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Step 6: Wait for FPGA to enter configuration phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_CFG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Step 7: Clear nSTATUS interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_GPIO_PORTA_EOI_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) SOCFPGA_FPGMGR_MON_NSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Step 8: Set CTRL.AXICFGEN to 1 to enable transfer of config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) socfpga_fpga_set_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) SOCFPGA_FPGMGR_CTL_AXICFGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Step 9: write data to the FPGA data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static int socfpga_fpga_ops_configure_write(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct socfpga_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 *buffer_32 = (u32 *)buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) size_t i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Write out the complete 32-bit chunks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) while (count >= sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) socfpga_fpga_data_writel(priv, buffer_32[i++]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) count -= sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Write out remaining non 32-bit chunks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) switch (count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x00ffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x0000ffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) socfpga_fpga_data_writel(priv, buffer_32[i++] & 0x000000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* This will never happen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int socfpga_fpga_ops_configure_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct socfpga_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * Step 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * - Observe CONF_DONE and nSTATUS (active low)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * - if CONF_DONE = 1 and nSTATUS = 1, configuration was successful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * - if CONF_DONE = 0 and nSTATUS = 0, configuration failed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) status = socfpga_fpga_wait_for_config_done(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Step 11: Clear CTRL.AXICFGEN to disable transfer of config data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SOCFPGA_FPGMGR_CTL_AXICFGEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * Step 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * - Write 4 to DCLKCNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * - Wait for STATUS.DCNTDONE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * - Clear W1C bit in STATUS.DCNTDONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (socfpga_fpga_dclk_set_and_wait_clear(priv, 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Step 13: Wait for STATUS.MODE to report USER MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (socfpga_fpga_wait_for_state(priv, SOCFPGA_FPGMGR_STAT_USER_MODE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Step 14: Set CTRL.EN to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) socfpga_fpga_clr_bitsl(priv, SOCFPGA_FPGMGR_CTL_OFST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SOCFPGA_FPGMGR_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Translate state register values to FPGA framework state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const enum fpga_mgr_states socfpga_state_to_framework_state[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [SOCFPGA_FPGMGR_STAT_POWER_OFF] = FPGA_MGR_STATE_POWER_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [SOCFPGA_FPGMGR_STAT_RESET] = FPGA_MGR_STATE_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [SOCFPGA_FPGMGR_STAT_CFG] = FPGA_MGR_STATE_WRITE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [SOCFPGA_FPGMGR_STAT_INIT] = FPGA_MGR_STATE_WRITE_INIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) [SOCFPGA_FPGMGR_STAT_USER_MODE] = FPGA_MGR_STATE_OPERATING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [SOCFPGA_FPGMGR_STAT_UNKNOWN] = FPGA_MGR_STATE_UNKNOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static enum fpga_mgr_states socfpga_fpga_ops_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct socfpga_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) enum fpga_mgr_states ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) state = socfpga_fpga_state_get(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (state < ARRAY_SIZE(socfpga_state_to_framework_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = socfpga_state_to_framework_state[state];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct fpga_manager_ops socfpga_fpga_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .state = socfpga_fpga_ops_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .write_init = socfpga_fpga_ops_configure_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .write = socfpga_fpga_ops_configure_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .write_complete = socfpga_fpga_ops_configure_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int socfpga_fpga_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct socfpga_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) priv->fpga_base_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (IS_ERR(priv->fpga_base_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return PTR_ERR(priv->fpga_base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) priv->fpga_data_addr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (IS_ERR(priv->fpga_data_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return PTR_ERR(priv->fpga_data_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) priv->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (priv->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return priv->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = devm_request_irq(dev, priv->irq, socfpga_fpga_isr, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_name(dev), priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mgr = devm_fpga_mgr_create(dev, "Altera SOCFPGA FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) &socfpga_fpga_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) platform_set_drvdata(pdev, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int socfpga_fpga_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct fpga_manager *mgr = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const struct of_device_id socfpga_fpga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { .compatible = "altr,socfpga-fpga-mgr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DEVICE_TABLE(of, socfpga_fpga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct platform_driver socfpga_fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .probe = socfpga_fpga_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .remove = socfpga_fpga_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .name = "socfpga_fpga_manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .of_match_table = of_match_ptr(socfpga_fpga_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) module_platform_driver(socfpga_fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MODULE_DESCRIPTION("Altera SOCFPGA FPGA Manager");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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