Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Lattice MachXO2 Slave SPI Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Manage Lattice FPGA firmware that is loaded over SPI using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * the slave serial configuration interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2018 Paolo Pisati <p.pisati@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* MachXO2 Programming Guide - sysCONFIG Programming Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IDCODE_PUB		{0xe0, 0x00, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define ISC_ENABLE		{0xc6, 0x08, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define ISC_ERASE		{0x0e, 0x04, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define ISC_PROGRAMDONE		{0x5e, 0x00, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LSC_INITADDRESS		{0x46, 0x00, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LSC_PROGINCRNV		{0x70, 0x00, 0x00, 0x01}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LSC_READ_STATUS		{0x3c, 0x00, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LSC_REFRESH		{0x79, 0x00, 0x00, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * Sheet' sysCONFIG Port Timing Specifications (3-36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MACHXO2_MAX_SPEED		66000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MACHXO2_LOW_DELAY_USEC		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MACHXO2_HIGH_DELAY_USEC		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MACHXO2_REFRESH_USEC		4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MACHXO2_MAX_BUSY_LOOP		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MACHXO2_MAX_REFRESH_LOOP	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MACHXO2_PAGE_SIZE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MACHXO2_BUF_SIZE		(MACHXO2_PAGE_SIZE + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Status register bits, errors and error mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BUSY	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DONE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DVER	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define ENAB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ERRBITS	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define ERRMASK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define FAIL	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ENOERR	0 /* no error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define EID	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define ECMD	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define ECRC	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define EPREAM	4 /* preamble error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define EABRT	5 /* abort error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define EOVERFL	6 /* overflow error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define ESDMEOF	7 /* SDM EOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static inline u8 get_err(unsigned long *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return (*status >> ERRBITS) & ERRMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int get_status(struct spi_device *spi, unsigned long *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct spi_transfer rx, tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	static const u8 cmd[] = LSC_READ_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	memset(&rx, 0, sizeof(rx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	memset(&tx, 0, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	tx.tx_buf = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	tx.len = sizeof(cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	rx.rx_buf = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	rx.len = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	spi_message_add_tail(&tx, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	spi_message_add_tail(&rx, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	*status = be32_to_cpu(*status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static const char *get_err_string(u8 err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	switch (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	case ENOERR:	return "No Error";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	case EID:	return "ID ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	case ECMD:	return "CMD ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case ECRC:	return "CRC ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	case EPREAM:	return "Preamble ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case EABRT:	return "Abort ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case EOVERFL:	return "Overflow ERR";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case ESDMEOF:	return "SDM EOF";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return "Default switch case";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void dump_status_reg(unsigned long *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	pr_debug("machxo2 status: 0x%08lX - done=%d, cfgena=%d, busy=%d, fail=%d, devver=%d, err=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		 *status, test_bit(DONE, status), test_bit(ENAB, status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		 test_bit(BUSY, status), test_bit(FAIL, status),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		 test_bit(DVER, status), get_err_string(get_err(status)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int wait_until_not_busy(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int ret, loop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		ret = get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		if (++loop >= MACHXO2_MAX_BUSY_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	} while (test_bit(BUSY, &status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int machxo2_cleanup(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct spi_device *spi = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	struct spi_transfer tx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	static const u8 erase[] = ISC_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	static const u8 refresh[] = LSC_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	memset(tx, 0, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	tx[0].tx_buf = &erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	tx[0].len = sizeof(erase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	spi_message_add_tail(&tx[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	ret = wait_until_not_busy(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	tx[1].tx_buf = &refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	tx[1].len = sizeof(refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	tx[1].delay.value = MACHXO2_REFRESH_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	spi_message_add_tail(&tx[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	dev_err(&mgr->dev, "Cleanup failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct spi_device *spi = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	    get_err(&status) == ENOERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return FPGA_MGR_STATE_OPERATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int machxo2_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			      struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			      const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct spi_device *spi = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct spi_transfer tx[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	static const u8 enable[] = ISC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	static const u8 erase[] = ISC_ERASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	static const u8 initaddr[] = LSC_INITADDRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		dev_err(&mgr->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 			"Partial reconfiguration is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	memset(tx, 0, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	tx[0].tx_buf = &enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	tx[0].len = sizeof(enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	tx[0].delay.value = MACHXO2_LOW_DELAY_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	tx[0].delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	spi_message_add_tail(&tx[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	tx[1].tx_buf = &erase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	tx[1].len = sizeof(erase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	spi_message_add_tail(&tx[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = wait_until_not_busy(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (test_bit(FAIL, &status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	tx[2].tx_buf = &initaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	tx[2].len = sizeof(initaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	spi_message_add_tail(&tx[2], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	dev_err(&mgr->dev, "Error during FPGA init.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int machxo2_write(struct fpga_manager *mgr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			 size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct spi_device *spi = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct spi_transfer tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	static const u8 progincr[] = LSC_PROGINCRNV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	u8 payload[MACHXO2_BUF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (count % MACHXO2_PAGE_SIZE != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		dev_err(&mgr->dev, "Malformed payload.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	memcpy(payload, &progincr, sizeof(progincr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		memcpy(&payload[sizeof(progincr)], &buf[i], MACHXO2_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		memset(&tx, 0, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		tx.tx_buf = payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		tx.len = MACHXO2_BUF_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		tx.delay.value = MACHXO2_HIGH_DELAY_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		tx.delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		spi_message_add_tail(&tx, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			dev_err(&mgr->dev, "Error loading the bitstream.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int machxo2_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				  struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct spi_device *spi = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct spi_message msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct spi_transfer tx[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	static const u8 progdone[] = ISC_PROGRAMDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	static const u8 refresh[] = LSC_REFRESH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	unsigned long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	int ret, refreshloop = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	memset(tx, 0, sizeof(tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	tx[0].tx_buf = &progdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	tx[0].len = sizeof(progdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	spi_message_add_tail(&tx[0], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ret = wait_until_not_busy(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (!test_bit(DONE, &status)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		machxo2_cleanup(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		spi_message_init(&msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		tx[1].tx_buf = &refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		tx[1].len = sizeof(refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		tx[1].delay.value = MACHXO2_REFRESH_USEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		tx[1].delay.unit = SPI_DELAY_UNIT_USECS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		spi_message_add_tail(&tx[1], &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		ret = spi_sync(spi, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		/* check refresh status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (!test_bit(BUSY, &status) && test_bit(DONE, &status) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		    get_err(&status) == ENOERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		if (++refreshloop == MACHXO2_MAX_REFRESH_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			machxo2_cleanup(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	get_status(spi, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	dump_status_reg(&status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	dev_err(&mgr->dev, "Refresh failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct fpga_manager_ops machxo2_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	.state = machxo2_spi_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	.write_init = machxo2_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.write = machxo2_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.write_complete = machxo2_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int machxo2_spi_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		dev_err(dev, "Speed is too high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	mgr = devm_fpga_mgr_create(dev, "Lattice MachXO2 SPI FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 				   &machxo2_ops, spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	spi_set_drvdata(spi, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int machxo2_spi_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	struct fpga_manager *mgr = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct of_device_id of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{ .compatible = "lattice,machxo2-slave-spi", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MODULE_DEVICE_TABLE(of, of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const struct spi_device_id lattice_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	{ "machxo2-slave-spi", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_DEVICE_TABLE(spi, lattice_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static struct spi_driver machxo2_spi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.name = "machxo2-slave-spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.of_match_table = of_match_ptr(of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.probe = machxo2_spi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.remove = machxo2_spi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.id_table = lattice_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) module_spi_driver(machxo2_spi_driver)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_AUTHOR("Paolo Pisati <p.pisati@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_LICENSE("GPL v2");