^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA Manager Driver for Lattice iCE40.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Joel Holdsworth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This driver adds support to the FPGA manager for configuring the SRAM of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Lattice iCE40 FPGAs through slave SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/stringify.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ICE40_SPI_MAX_SPEED 25000000 /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ICE40_SPI_MIN_SPEED 1000000 /* Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ICE40_SPI_RESET_DELAY 1 /* us (>200ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ICE40_SPI_HOUSEKEEPING_DELAY 1200 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ICE40_SPI_NUM_ACTIVATION_BYTES DIV_ROUND_UP(49, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ice40_fpga_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct spi_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct gpio_desc *cdone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static enum fpga_mgr_states ice40_fpga_ops_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct ice40_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return gpiod_get_value(priv->cdone) ? FPGA_MGR_STATE_OPERATING :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct ice40_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct spi_device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct spi_message message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct spi_transfer assert_cs_then_reset_delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .cs_change = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .value = ICE40_SPI_RESET_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct spi_transfer housekeeping_delay_then_release_cs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .delay = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .value = ICE40_SPI_HOUSEKEEPING_DELAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .unit = SPI_DELAY_UNIT_USECS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "Partial reconfiguration is not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) spi_bus_lock(dev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) gpiod_set_value(priv->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) spi_message_add_tail(&assert_cs_then_reset_delay, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ret = spi_sync_locked(dev, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Come out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) gpiod_set_value(priv->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Abort if the chip-select failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Check CDONE is de-asserted i.e. the FPGA is reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (gpiod_get_value(priv->cdone)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) goto fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Wait for the housekeeping to complete, and release SS_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spi_message_init(&message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = spi_sync_locked(dev, &message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spi_bus_unlock(dev->master);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int ice40_fpga_ops_write(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ice40_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return spi_write(priv->dev, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ice40_fpga_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct spi_device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Check CDONE is asserted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!gpiod_get_value(priv->cdone)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "CDONE was not asserted after firmware transfer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Send of zero-padding to activate the firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return spi_write(dev, padding, sizeof(padding));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct fpga_manager_ops ice40_fpga_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .state = ice40_fpga_ops_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .write_init = ice40_fpga_ops_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .write = ice40_fpga_ops_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .write_complete = ice40_fpga_ops_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int ice40_fpga_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct ice40_fpga_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) priv->dev = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Check board setup data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dev_err(dev, "SPI speed is too high, maximum speed is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __stringify(ICE40_SPI_MAX_SPEED) "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dev_err(dev, "SPI speed is too low, minimum speed is "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __stringify(ICE40_SPI_MIN_SPEED) "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (spi->mode & SPI_CPHA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dev_err(dev, "Bad SPI mode, CPHA not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Set up the GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (IS_ERR(priv->cdone)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ret = PTR_ERR(priv->cdone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (IS_ERR(priv->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = PTR_ERR(priv->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) mgr = devm_fpga_mgr_create(dev, "Lattice iCE40 FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &ice40_fpga_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) spi_set_drvdata(spi, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int ice40_fpga_remove(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct fpga_manager *mgr = spi_get_drvdata(spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct of_device_id ice40_fpga_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .compatible = "lattice,ice40-fpga-mgr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MODULE_DEVICE_TABLE(of, ice40_fpga_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct spi_driver ice40_fpga_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .probe = ice40_fpga_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .remove = ice40_fpga_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "ice40spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .of_match_table = of_match_ptr(ice40_fpga_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) module_spi_driver(ice40_fpga_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MODULE_AUTHOR("Joel Holdsworth <joel@airwebreathe.org.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MODULE_DESCRIPTION("Lattice iCE40 FPGA Manager");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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