^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA Manager Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013-2015 Altera Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * With code from the mailing list:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2013 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static DEFINE_IDA(fpga_mgr_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct class *fpga_mgr_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * fpga_image_info_alloc - Allocate a FPGA image info struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @dev: owning device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Return: struct fpga_image_info or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct fpga_image_info *fpga_image_info_alloc(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct fpga_image_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) get_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) info->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) EXPORT_SYMBOL_GPL(fpga_image_info_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * fpga_image_info_free - Free a FPGA image info struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @info: FPGA image info struct to free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) void fpga_image_info_free(struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev = info->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (info->firmware_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) devm_kfree(dev, info->firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) devm_kfree(dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) EXPORT_SYMBOL_GPL(fpga_image_info_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * Call the low level driver's write_init function. This will do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * device-specific things to get the FPGA into the state where it is ready to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * receive an FPGA image. The low level driver only gets to see the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * initial_header_size bytes in the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mgr->state = FPGA_MGR_STATE_WRITE_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!mgr->mops->initial_header_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = mgr->mops->write_init(mgr, info, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = mgr->mops->write_init(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mgr, info, buf, min(mgr->mops->initial_header_size, count));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct sg_table *sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct sg_mapping_iter miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) char *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!mgr->mops->initial_header_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * First try to use miter to map the first fragment to access the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * header, this is the typical path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (sg_miter_next(&miter) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) miter.length >= mgr->mops->initial_header_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) miter.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Otherwise copy the fragments into temporary memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mgr->mops->initial_header_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) kfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * After all the FPGA image has been written, do the device specific steps to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * finish and set the FPGA into operating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int fpga_mgr_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) ret = mgr->mops->write_complete(mgr, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) mgr->state = FPGA_MGR_STATE_OPERATING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @info: fpga image specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @sgt: scatterlist table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Step the low level fpga manager through the device-specific steps of getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * an FPGA ready to be configured, writing the image to it, then doing whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * post-configuration steps necessary. This code assumes the caller got the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * not an error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * This is the preferred entry point for FPGA programming, it does not require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * any contiguous kernel memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Return: 0 on success, negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct sg_table *sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = fpga_mgr_write_init_sg(mgr, info, sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Write the FPGA image to the FPGA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mgr->state = FPGA_MGR_STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (mgr->mops->write_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = mgr->mops->write_sg(mgr, sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct sg_mapping_iter miter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (sg_miter_next(&miter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = mgr->mops->write(mgr, miter.addr, miter.length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sg_miter_stop(&miter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mgr->state = FPGA_MGR_STATE_WRITE_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return fpga_mgr_write_complete(mgr, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Write the FPGA image to the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mgr->state = FPGA_MGR_STATE_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = mgr->mops->write(mgr, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mgr->state = FPGA_MGR_STATE_WRITE_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return fpga_mgr_write_complete(mgr, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * fpga_mgr_buf_load - load fpga from image in buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @info: fpga image info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @buf: buffer contain fpga image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @count: byte count of buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * Step the low level fpga manager through the device-specific steps of getting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * an FPGA ready to be configured, writing the image to it, then doing whatever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * post-configuration steps necessary. This code assumes the caller got the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * Return: 0 on success, negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int fpga_mgr_buf_load(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct page **pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct sg_table sgt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const void *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int nr_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * This is just a fast path if the caller has already created a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * contiguous kernel buffer and the driver doesn't require SG, non-SG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * drivers will still work on the slow path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (mgr->mops->write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Convert the linear kernel pointer into a sg_table of pages for use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (unsigned long)buf / PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) p = buf - offset_in_page(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) for (index = 0; index < nr_pages; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (is_vmalloc_addr(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pages[index] = vmalloc_to_page(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pages[index] = kmap_to_page((void *)p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!pages[index]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) kfree(pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) p += PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * The temporary pages list is used to code share the merging algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * in sg_alloc_table_from_pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) count, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) kfree(pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) sg_free_table(&sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * fpga_mgr_firmware_load - request firmware and load to fpga
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @info: fpga image specific information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @image_name: name of image file on the firmware search path
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Request an FPGA image using the firmware class, then write out to the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Update the state before each step to provide info on what step failed if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * there is a failure. This code assumes the caller got the mgr pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Return: 0 on success, negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int fpga_mgr_firmware_load(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) const char *image_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct device *dev = &mgr->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ret = request_firmware(&fw, image_name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(dev, "Error requesting firmware %s\n", image_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * fpga_mgr_load - load FPGA from scatter/gather table, buffer, or firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @info: fpga image information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * Load the FPGA from an image which is indicated in @info. If successful, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * FPGA ends up in operating mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * Return: 0 on success, negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int fpga_mgr_load(struct fpga_manager *mgr, struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (info->sgt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return fpga_mgr_buf_load_sg(mgr, info, info->sgt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (info->buf && info->count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return fpga_mgr_buf_load(mgr, info, info->buf, info->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (info->firmware_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return fpga_mgr_firmware_load(mgr, info, info->firmware_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EXPORT_SYMBOL_GPL(fpga_mgr_load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const char * const state_str[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [FPGA_MGR_STATE_UNKNOWN] = "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [FPGA_MGR_STATE_POWER_OFF] = "power off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [FPGA_MGR_STATE_POWER_UP] = "power up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [FPGA_MGR_STATE_RESET] = "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* requesting FPGA image from firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Preparing FPGA to receive image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [FPGA_MGR_STATE_WRITE_INIT] = "write init",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Writing image to FPGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [FPGA_MGR_STATE_WRITE] = "write",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [FPGA_MGR_STATE_WRITE_ERR] = "write error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Finishing configuration after image has been written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* FPGA reports to be in normal operating mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) [FPGA_MGR_STATE_OPERATING] = "operating",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static ssize_t name_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct fpga_manager *mgr = to_fpga_manager(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return sprintf(buf, "%s\n", mgr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static ssize_t state_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct fpga_manager *mgr = to_fpga_manager(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return sprintf(buf, "%s\n", state_str[mgr->state]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static ssize_t status_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct fpga_manager *mgr = to_fpga_manager(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!mgr->mops->status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) status = mgr->mops->status(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (status & FPGA_MGR_STATUS_OPERATION_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) len += sprintf(buf + len, "reconfig operation error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (status & FPGA_MGR_STATUS_CRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) len += sprintf(buf + len, "reconfig CRC error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (status & FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) len += sprintf(buf + len, "reconfig incompatible image\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (status & FPGA_MGR_STATUS_IP_PROTOCOL_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) len += sprintf(buf + len, "reconfig IP protocol error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (status & FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) len += sprintf(buf + len, "reconfig fifo overflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static DEVICE_ATTR_RO(name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static DEVICE_ATTR_RO(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static DEVICE_ATTR_RO(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static struct attribute *fpga_mgr_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &dev_attr_name.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &dev_attr_state.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) &dev_attr_status.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ATTRIBUTE_GROUPS(fpga_mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct fpga_manager *__fpga_mgr_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mgr = to_fpga_manager(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!try_module_get(dev->parent->driver->owner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto err_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) err_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int fpga_mgr_dev_match(struct device *dev, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return dev->parent == data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * fpga_mgr_get - Given a device, get a reference to a fpga mgr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * @dev: parent device that fpga mgr was registered with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Return: fpga manager struct or IS_ERR() condition containing error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct fpga_manager *fpga_mgr_get(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) fpga_mgr_dev_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!mgr_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return __fpga_mgr_get(mgr_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) EXPORT_SYMBOL_GPL(fpga_mgr_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * of_fpga_mgr_get - Given a device node, get a reference to a fpga mgr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * @node: device node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * Return: fpga manager struct or IS_ERR() condition containing error code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev = class_find_device_by_of_node(fpga_mgr_class, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return __fpga_mgr_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * fpga_mgr_put - release a reference to a fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @mgr: fpga manager structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) void fpga_mgr_put(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) module_put(mgr->dev.parent->driver->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) put_device(&mgr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) EXPORT_SYMBOL_GPL(fpga_mgr_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * fpga_mgr_lock - Lock FPGA manager for exclusive use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * Given a pointer to FPGA Manager (from fpga_mgr_get() or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * of_fpga_mgr_put()) attempt to get the mutex. The user should call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * fpga_mgr_lock() and verify that it returns 0 before attempting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * program the FPGA. Likewise, the user should call fpga_mgr_unlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * when done programming the FPGA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * Return: 0 for success or -EBUSY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int fpga_mgr_lock(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!mutex_trylock(&mgr->ref_mutex)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(&mgr->dev, "FPGA manager is in use.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) EXPORT_SYMBOL_GPL(fpga_mgr_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * fpga_mgr_unlock - Unlock FPGA manager after done programming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @mgr: fpga manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) void fpga_mgr_unlock(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mutex_unlock(&mgr->ref_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) EXPORT_SYMBOL_GPL(fpga_mgr_unlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * fpga_mgr_create - create and initialize a FPGA manager struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @dev: fpga manager device from pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @name: fpga manager name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * @mops: pointer to structure of fpga manager ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * @priv: fpga manager private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * The caller of this function is responsible for freeing the struct with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * fpga_mgr_free(). Using devm_fpga_mgr_create() instead is recommended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * Return: pointer to struct fpga_manager or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct fpga_manager *fpga_mgr_create(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct fpga_manager_ops *mops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (!mops || !mops->write_complete || !mops->state ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) !mops->write_init || (!mops->write && !mops->write_sg) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) (mops->write && mops->write_sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dev_err(dev, "Attempt to register without fpga_manager_ops\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (!name || !strlen(name)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(dev, "Attempt to register with no name!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (id < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) goto error_kfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mutex_init(&mgr->ref_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mgr->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) mgr->mops = mops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mgr->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) device_initialize(&mgr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mgr->dev.class = fpga_mgr_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mgr->dev.groups = mops->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mgr->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mgr->dev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mgr->dev.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ret = dev_set_name(&mgr->dev, "fpga%d", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) goto error_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) error_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ida_simple_remove(&fpga_mgr_ida, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) error_kfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) kfree(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) EXPORT_SYMBOL_GPL(fpga_mgr_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * fpga_mgr_free - free a FPGA manager created with fpga_mgr_create()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @mgr: fpga manager struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) void fpga_mgr_free(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kfree(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) EXPORT_SYMBOL_GPL(fpga_mgr_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static void devm_fpga_mgr_release(struct device *dev, void *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct fpga_manager *mgr = *(struct fpga_manager **)res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) fpga_mgr_free(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * devm_fpga_mgr_create - create and initialize a managed FPGA manager struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * @dev: fpga manager device from pdev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * @name: fpga manager name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * @mops: pointer to structure of fpga manager ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * @priv: fpga manager private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * This function is intended for use in a FPGA manager driver's probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * After the manager driver creates the manager struct with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * devm_fpga_mgr_create(), it should register it with fpga_mgr_register(). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * manager driver's remove function should call fpga_mgr_unregister(). The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * manager struct allocated with this function will be freed automatically on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * driver detach. This includes the case of a probe function returning error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * before calling fpga_mgr_register(), the struct will still get cleaned up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Return: pointer to struct fpga_manager or NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct fpga_manager *devm_fpga_mgr_create(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const struct fpga_manager_ops *mops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct fpga_manager **ptr, *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ptr = devres_alloc(devm_fpga_mgr_release, sizeof(*ptr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mgr = fpga_mgr_create(dev, name, mops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!mgr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) devres_free(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *ptr = mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) devres_add(dev, ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) EXPORT_SYMBOL_GPL(devm_fpga_mgr_create);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * fpga_mgr_register - register a FPGA manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @mgr: fpga manager struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * Return: 0 on success, negative error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int fpga_mgr_register(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Initialize framework state by requesting low level driver read state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * from device. FPGA may be in reset mode or may have been programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * by bootloader or EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mgr->state = mgr->mops->state(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ret = device_add(&mgr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto error_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) dev_info(&mgr->dev, "%s registered\n", mgr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) error_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EXPORT_SYMBOL_GPL(fpga_mgr_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * fpga_mgr_unregister - unregister a FPGA manager
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * @mgr: fpga manager struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * This function is intended for use in a FPGA manager driver's remove function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) void fpga_mgr_unregister(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * If the low level driver provides a method for putting fpga into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * a desired state upon unregister, do it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (mgr->mops->fpga_remove)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) mgr->mops->fpga_remove(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) device_unregister(&mgr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static void fpga_mgr_dev_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static int __init fpga_mgr_class_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_info("FPGA manager framework\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (IS_ERR(fpga_mgr_class))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return PTR_ERR(fpga_mgr_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) fpga_mgr_class->dev_groups = fpga_mgr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) fpga_mgr_class->dev_release = fpga_mgr_dev_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void __exit fpga_mgr_class_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) class_destroy(fpga_mgr_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ida_destroy(&fpga_mgr_ida);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MODULE_AUTHOR("Alan Tull <atull@kernel.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_DESCRIPTION("FPGA manager framework");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) subsys_initcall(fpga_mgr_class_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) module_exit(fpga_mgr_class_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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