^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Device Feature List (DFL) PCIe device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Zhang Yi <Yi.Z.Zhang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "dfl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRV_VERSION "0.8"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRV_NAME "dfl-pci"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct cci_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct dfl_fpga_cdev *cdev; /* container device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return pcim_iomap_table(pcidev)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int cci_pci_alloc_irq(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int ret, nvec = pci_msix_vec_count(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (nvec <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void cci_pci_free_irq(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pci_free_irq_vectors(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* PCI Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* VF Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static struct pci_device_id cci_pcie_id_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static int cci_init_drvdata(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct cci_drvdata *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pci_set_drvdata(pcidev, drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void cci_remove_feature_devs(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* remove all children feature devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dfl_fpga_feature_devs_remove(drvdata->cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) cci_pci_free_irq(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) int *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (!table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) for (i = 0; i < nvec; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) table[i] = pci_irq_vector(pcidev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* enumerate feature devices under pci device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int port_num, bar, i, nvec, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct dfl_fpga_enum_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct dfl_fpga_cdev *cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) resource_size_t start, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int *irq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* allocate enumeration info via pci_dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) info = dfl_fpga_enum_info_alloc(&pcidev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* add irq info for enumeration if the device support irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) nvec = cci_pci_alloc_irq(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (nvec < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = nvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) goto enum_info_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) } else if (nvec) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) irq_table = cci_pci_create_irq_table(pcidev, nvec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!irq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) goto irq_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) kfree(irq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) goto irq_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* start to find Device Feature List in Bar 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) base = cci_pci_ioremap_bar0(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto irq_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * PF device has FME and Ports/AFUs, and VF device only has one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Port/AFU. Check them and add related "Device Feature List" info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * for the next step enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (dfl_feature_is_fme(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) start = pci_resource_start(pcidev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) len = pci_resource_len(pcidev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) dfl_fpga_enum_info_add_dfl(info, start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * find more Device Feature Lists (e.g. Ports) per information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * indicated by FME module.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) v = readq(base + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < port_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v = readq(base + FME_HDR_PORT_OFST(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* skip ports which are not implemented. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!(v & FME_PORT_OFST_IMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * add Port's Device Feature List information for next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * step enumeration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) start = pci_resource_start(pcidev, bar) + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) len = pci_resource_len(pcidev, bar) - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dfl_fpga_enum_info_add_dfl(info, start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) } else if (dfl_feature_is_port(base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) start = pci_resource_start(pcidev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) len = pci_resource_len(pcidev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dfl_fpga_enum_info_add_dfl(info, start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto irq_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* release I/O mappings for next step enumeration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pcim_iounmap_regions(pcidev, BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* start enumeration with prepared enumeration information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) cdev = dfl_fpga_feature_devs_enumerate(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (IS_ERR(cdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) dev_err(&pcidev->dev, "Enumeration failure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = PTR_ERR(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) goto irq_free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) drvdata->cdev = cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) irq_free_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) cci_pci_free_irq(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) enum_info_free_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dfl_fpga_enum_info_free(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = pcim_enable_device(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = pci_enable_pcie_error_reporting(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret && ret != -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dev_info(&pcidev->dev, "PCIE AER unavailable %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_set_master(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(64))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) goto disable_error_report_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) } else if (!pci_set_dma_mask(pcidev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) goto disable_error_report_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(&pcidev->dev, "No suitable DMA support available.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) goto disable_error_report_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = cci_init_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) goto disable_error_report_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) ret = cci_enumerate_feature_devs(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) disable_error_report_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) pci_disable_pcie_error_reporting(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct dfl_fpga_cdev *cdev = drvdata->cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!num_vfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * disable SRIOV and then put released ports back to default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * PF access mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pci_disable_sriov(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dfl_fpga_cdev_config_ports_pf(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * before enable SRIOV, put released ports into VF access mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * first of all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = pci_enable_sriov(pcidev, num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) dfl_fpga_cdev_config_ports_pf(cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return num_vfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void cci_pci_remove(struct pci_dev *pcidev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (dev_is_pf(&pcidev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) cci_pci_sriov_configure(pcidev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) cci_remove_feature_devs(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) pci_disable_pcie_error_reporting(pcidev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct pci_driver cci_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = DRV_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .id_table = cci_pcie_id_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .probe = cci_pci_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .remove = cci_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .sriov_configure = cci_pci_sriov_configure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) module_pci_driver(cci_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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