Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Header file for FPGA Management Engine (FME) Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *   Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *   Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *   Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *   Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *   Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *   Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __DFL_FME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __DFL_FME_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * struct dfl_fme - dfl fme private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @mgr: FME's FPGA manager platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * @region_list: linked list of FME's FPGA regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * @bridge_list: linked list of FME's FPGA bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * @pdata: fme platform device's pdata.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct dfl_fme {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	struct platform_device *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct list_head region_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct list_head bridge_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct dfl_feature_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) extern const struct dfl_feature_ops fme_pr_mgmt_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern const struct dfl_feature_ops fme_global_err_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) extern const struct dfl_feature_id fme_global_err_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) extern const struct attribute_group fme_global_err_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) extern const struct dfl_feature_ops fme_perf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern const struct dfl_feature_id fme_perf_id_table[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif /* __DFL_FME_H */