Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * FPGA Region Driver for FPGA Management Engine (FME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *   Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *   Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *   Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *   Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fpga/fpga-region.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "dfl-fme-pr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int fme_region_get_bridges(struct fpga_region *region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	struct dfl_fme_region_pdata *pdata = region->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	struct device *dev = &pdata->br->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	return fpga_bridge_get_to_list(dev, region->info, &region->bridge_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int fme_region_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct dfl_fme_region_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	struct fpga_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	mgr = fpga_mgr_get(&pdata->mgr->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	if (IS_ERR(mgr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	region = devm_fpga_region_create(dev, mgr, fme_region_get_bridges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	if (!region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		goto eprobe_mgr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	region->priv = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	region->compat_id = mgr->compat_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	platform_set_drvdata(pdev, region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	ret = fpga_region_register(region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		goto eprobe_mgr_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	dev_dbg(dev, "DFL FME FPGA Region probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) eprobe_mgr_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	fpga_mgr_put(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static int fme_region_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	struct fpga_region *region = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	struct fpga_manager *mgr = region->mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	fpga_region_unregister(region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	fpga_mgr_put(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static struct platform_driver fme_region_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 		.name    = DFL_FPGA_FME_REGION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	.probe   = fme_region_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	.remove  = fme_region_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) module_platform_driver(fme_region_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_DESCRIPTION("FPGA Region for DFL FPGA Management Engine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_ALIAS("platform:dfl-fme-region");