Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Header file for FPGA Management Engine (FME) Partial Reconfiguration Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  *   Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *   Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  *   Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *   Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *   Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *   Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef __DFL_FME_PR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define __DFL_FME_PR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * struct dfl_fme_region - FME fpga region data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * @region: platform device of the FPGA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * @node: used to link fme_region to a list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  * @port_id: indicate which port this region connected to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct dfl_fme_region {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct platform_device *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * struct dfl_fme_region_pdata - platform data for FME region platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @mgr: platform device of the FPGA manager.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @br: platform device of the FPGA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * @region_id: region id (same as port_id).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct dfl_fme_region_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	struct platform_device *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	struct platform_device *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	int region_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)  * struct dfl_fme_bridge - FME fpga bridge data structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)  * @br: platform device of the FPGA bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * @node: used to link fme_bridge to a list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct dfl_fme_bridge {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	struct platform_device *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * struct dfl_fme_bridge_pdata - platform data for FME bridge platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  * @cdev: container device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  * @port_id: port id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct dfl_fme_br_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	struct dfl_fpga_cdev *cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)  * struct dfl_fme_mgr_pdata - platform data for FME manager platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)  * @ioaddr: mapped io address for FME manager platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dfl_fme_mgr_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DFL_FPGA_FME_MGR	"dfl-fme-mgr"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DFL_FPGA_FME_BRIDGE	"dfl-fme-bridge"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DFL_FPGA_FME_REGION	"dfl-fme-region"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* __DFL_FME_PR_H */