^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Management Engine (FME) Partial Reconfiguration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Christopher Rauer <christopher.rauer@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/fpga/fpga-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/fpga/fpga-region.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/fpga-dfl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "dfl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "dfl-fme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "dfl-fme-pr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct dfl_fme_region *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dfl_fme_region_find_by_port_id(struct dfl_fme *fme, int port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct dfl_fme_region *fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) list_for_each_entry(fme_region, &fme->region_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (fme_region->port_id == port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int dfl_fme_region_match(struct device *dev, const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return dev->parent == data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static struct fpga_region *dfl_fme_region_find(struct dfl_fme *fme, int port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct dfl_fme_region *fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct fpga_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) fme_region = dfl_fme_region_find_by_port_id(fme, port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!fme_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) region = fpga_region_class_find(NULL, &fme_region->region->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dfl_fme_region_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if (!region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int fme_pr(struct platform_device *pdev, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) void __user *argp = (void __user *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dfl_fpga_fme_port_pr port_pr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct fpga_image_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct fpga_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) void __iomem *fme_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct dfl_fme *fme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) void *buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) minsz = offsetofend(struct dfl_fpga_fme_port_pr, buffer_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (copy_from_user(&port_pr, argp, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (port_pr.argsz < minsz || port_pr.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* get fme header region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* check port id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) v = readq(fme_hdr + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (port_pr.port_id >= FIELD_GET(FME_CAP_NUM_PORTS, v)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_dbg(&pdev->dev, "port number more than maximum\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * align PR buffer per PR bandwidth, as HW ignores the extra padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * data automatically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) length = ALIGN(port_pr.buffer_size, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) buf = vmalloc(length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (copy_from_user(buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (void __user *)(unsigned long)port_pr.buffer_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) port_pr.buffer_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* prepare fpga_image_info for PR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) info = fpga_image_info_alloc(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto free_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) info->flags |= FPGA_MGR_PARTIAL_RECONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) fme = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* fme device has been unregistered. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!fme) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto unlock_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) region = dfl_fme_region_find(fme, port_pr.port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!region) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) goto unlock_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) fpga_image_info_free(region->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) info->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) info->count = length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) info->region_id = port_pr.port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) region->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) ret = fpga_region_program_fpga(region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * it allows userspace to reset the PR region's logic by disabling and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * reenabling the bridge to clear things out between accleration runs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * so no need to hold the bridges after partial reconfiguration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (region->get_bridges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) fpga_bridges_put(®ion->bridge_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) put_device(®ion->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unlock_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) free_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) vfree(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * dfl_fme_create_mgr - create fpga mgr platform device as child device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @pdata: fme platform_device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * Return: mgr platform device if successful, and error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct platform_device *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dfl_fme_create_mgr(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct platform_device *mgr, *fme = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dfl_fme_mgr_pdata mgr_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!feature->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) mgr_pdata.ioaddr = feature->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * Each FME has only one fpga-mgr, so allocate platform device using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * the same FME platform device id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mgr = platform_device_alloc(DFL_FPGA_FME_MGR, fme->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) mgr->dev.parent = &fme->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = platform_device_add_data(mgr, &mgr_pdata, sizeof(mgr_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) goto create_mgr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ret = platform_device_add(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) goto create_mgr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) create_mgr_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) platform_device_put(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * dfl_fme_destroy_mgr - destroy fpga mgr platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @pdata: fme platform device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void dfl_fme_destroy_mgr(struct dfl_feature_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) platform_device_unregister(priv->mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * dfl_fme_create_bridge - create fme fpga bridge platform device as child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @pdata: fme platform device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @port_id: port id for the bridge to be created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * Return: bridge platform device if successful, and error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct dfl_fme_bridge *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) dfl_fme_create_bridge(struct dfl_feature_platform_data *pdata, int port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct device *dev = &pdata->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dfl_fme_br_pdata br_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct dfl_fme_bridge *fme_br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) fme_br = devm_kzalloc(dev, sizeof(*fme_br), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!fme_br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) br_pdata.cdev = pdata->dfl_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) br_pdata.port_id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) fme_br->br = platform_device_alloc(DFL_FPGA_FME_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PLATFORM_DEVID_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!fme_br->br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) fme_br->br->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ret = platform_device_add_data(fme_br->br, &br_pdata, sizeof(br_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) goto create_br_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = platform_device_add(fme_br->br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto create_br_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return fme_br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) create_br_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) platform_device_put(fme_br->br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * dfl_fme_destroy_bridge - destroy fpga bridge platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @fme_br: fme bridge to destroy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static void dfl_fme_destroy_bridge(struct dfl_fme_bridge *fme_br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) platform_device_unregister(fme_br->br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * dfl_fme_destroy_bridge - destroy all fpga bridge platform device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @pdata: fme platform device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void dfl_fme_destroy_bridges(struct dfl_feature_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct dfl_fme_bridge *fbridge, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) list_for_each_entry_safe(fbridge, tmp, &priv->bridge_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) list_del(&fbridge->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dfl_fme_destroy_bridge(fbridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * dfl_fme_create_region - create fpga region platform device as child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @pdata: fme platform device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @mgr: mgr platform device needed for region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @br: br platform device needed for region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @port_id: port id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * Return: fme region if successful, and error code otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct dfl_fme_region *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dfl_fme_create_region(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct platform_device *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct platform_device *br, int port_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct dfl_fme_region_pdata region_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct device *dev = &pdata->dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct dfl_fme_region *fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) fme_region = devm_kzalloc(dev, sizeof(*fme_region), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!fme_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) region_pdata.mgr = mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) region_pdata.br = br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Each FPGA device may have more than one port, so allocate platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * device using the same port platform device id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) fme_region->region = platform_device_alloc(DFL_FPGA_FME_REGION, br->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (!fme_region->region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) fme_region->region->dev.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = platform_device_add_data(fme_region->region, ®ion_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) sizeof(region_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) goto create_region_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ret = platform_device_add(fme_region->region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto create_region_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) fme_region->port_id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) create_region_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) platform_device_put(fme_region->region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * dfl_fme_destroy_region - destroy fme region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @fme_region: fme region to destroy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void dfl_fme_destroy_region(struct dfl_fme_region *fme_region)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) platform_device_unregister(fme_region->region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * dfl_fme_destroy_regions - destroy all fme regions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @pdata: fme platform device's pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void dfl_fme_destroy_regions(struct dfl_feature_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct dfl_fme *priv = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct dfl_fme_region *fme_region, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) list_for_each_entry_safe(fme_region, tmp, &priv->region_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) list_del(&fme_region->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dfl_fme_destroy_region(fme_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int pr_mgmt_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dfl_fme_region *fme_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct dfl_fme_bridge *fme_br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct platform_device *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct dfl_fme *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) void __iomem *fme_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret = -ENODEV, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) u64 fme_cap, port_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fme_hdr = dfl_get_feature_ioaddr_by_id(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) priv = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Initialize the region and bridge sub device list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) INIT_LIST_HEAD(&priv->region_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) INIT_LIST_HEAD(&priv->bridge_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Create fpga mgr platform device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mgr = dfl_fme_create_mgr(pdata, feature);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (IS_ERR(mgr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_err(&pdev->dev, "fail to create fpga mgr pdev\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) priv->mgr = mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Read capability register to check number of regions and bridges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fme_cap = readq(fme_hdr + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) for (; i < FIELD_GET(FME_CAP_NUM_PORTS, fme_cap); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) port_offset = readq(fme_hdr + FME_HDR_PORT_OFST(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!(port_offset & FME_PORT_OFST_IMP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Create bridge for each port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) fme_br = dfl_fme_create_bridge(pdata, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (IS_ERR(fme_br)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = PTR_ERR(fme_br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) goto destroy_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) list_add(&fme_br->node, &priv->bridge_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Create region for each port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) fme_region = dfl_fme_create_region(pdata, mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) fme_br->br, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (IS_ERR(fme_region)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = PTR_ERR(fme_region);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) goto destroy_region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) list_add(&fme_region->node, &priv->region_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) destroy_region:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dfl_fme_destroy_regions(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dfl_fme_destroy_bridges(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dfl_fme_destroy_mgr(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void pr_mgmt_uinit(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dfl_fme_destroy_regions(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dfl_fme_destroy_bridges(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dfl_fme_destroy_mgr(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static long fme_pr_ioctl(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case DFL_FPGA_FME_PORT_PR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ret = fme_pr(pdev, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct dfl_feature_id fme_pr_mgmt_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {.id = FME_FEATURE_ID_PR_MGMT,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) const struct dfl_feature_ops fme_pr_mgmt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .init = pr_mgmt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .uinit = pr_mgmt_uinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .ioctl = fme_pr_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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