^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * FPGA Manager Driver for FPGA Management Engine (FME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Christopher Rauer <christopher.rauer@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/fpga/fpga-mgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "dfl-fme-pr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* FME Partial Reconfiguration Sub Feature Register Set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FME_PR_DFH 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FME_PR_CTRL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FME_PR_STS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FME_PR_DATA 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FME_PR_ERR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FME_PR_INTFC_ID_L 0xA8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FME_PR_INTFC_ID_H 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* FME PR Control Register Bitfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* FME PR Status Register Bitfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Number of available entries in HW queue inside the PR engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FME_PR_STS_PR_CREDIT GENMASK_ULL(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FME_PR_STS_PR_STS BIT_ULL(16) /* PR operation status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FME_PR_STS_PR_STS_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define FME_PR_STS_PR_CTRLR_STS GENMASK_ULL(22, 20) /* Controller status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FME_PR_STS_PR_HOST_STS GENMASK_ULL(27, 24) /* PR host status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* FME PR Data Register Bitfield */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PR data from the raw-binary file. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define FME_PR_DATA_PR_DATA_RAW GENMASK_ULL(32, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* FME PR Error Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* PR Operation errors detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FME_PR_ERR_OPERATION_ERR BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* CRC error detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define FME_PR_ERR_CRC_ERR BIT_ULL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Incompatible PR bitstream detected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define FME_PR_ERR_INCOMPATIBLE_BS BIT_ULL(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* PR data push protocol violated. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define FME_PR_ERR_PROTOCOL_ERR BIT_ULL(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* PR data fifo overflow error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define FME_PR_ERR_FIFO_OVERFLOW BIT_ULL(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PR_WAIT_TIMEOUT 8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PR_HOST_STATUS_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct fme_mgr_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u64 pr_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static u64 pr_error_to_mgr_status(u64 err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u64 status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (err & FME_PR_ERR_OPERATION_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) status |= FPGA_MGR_STATUS_OPERATION_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (err & FME_PR_ERR_CRC_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) status |= FPGA_MGR_STATUS_CRC_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (err & FME_PR_ERR_INCOMPATIBLE_BS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) status |= FPGA_MGR_STATUS_INCOMPATIBLE_IMAGE_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (err & FME_PR_ERR_PROTOCOL_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) status |= FPGA_MGR_STATUS_IP_PROTOCOL_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (err & FME_PR_ERR_FIFO_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) status |= FPGA_MGR_STATUS_FIFO_OVERFLOW_ERR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static u64 fme_mgr_pr_error_handle(void __iomem *fme_pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 pr_status, pr_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) pr_status = readq(fme_pr + FME_PR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (!(pr_status & FME_PR_STS_PR_STS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) pr_error = readq(fme_pr + FME_PR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) writeq(pr_error, fme_pr + FME_PR_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return pr_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int fme_mgr_write_init(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct fpga_image_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct device *dev = &mgr->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct fme_mgr_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *fme_pr = priv->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u64 pr_ctrl, pr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dev_err(dev, "only supports partial reconfiguration.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_dbg(dev, "resetting PR before initiated PR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pr_ctrl = readq(fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_ctrl |= FME_PR_CTRL_PR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pr_ctrl & FME_PR_CTRL_PR_RSTACK, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PR_WAIT_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dev_err(dev, "PR Reset ACK timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pr_ctrl = readq(fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_ctrl &= ~FME_PR_CTRL_PR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) "waiting for PR resource in HW to be initialized and ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (readq_poll_timeout(fme_pr + FME_PR_STS, pr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (pr_status & FME_PR_STS_PR_STS) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FME_PR_STS_PR_STS_IDLE, 1, PR_WAIT_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(dev, "PR Status timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dev_dbg(dev, "check and clear previous PR error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (priv->pr_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dev_dbg(dev, "previous PR error detected %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) (unsigned long long)priv->pr_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dev_dbg(dev, "set PR port ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pr_ctrl = readq(fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pr_ctrl &= ~FME_PR_CTRL_PR_RGN_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) pr_ctrl |= FIELD_PREP(FME_PR_CTRL_PR_RGN_ID, info->region_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static int fme_mgr_write(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct device *dev = &mgr->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct fme_mgr_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void __iomem *fme_pr = priv->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 pr_ctrl, pr_status, pr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int delay = 0, pr_credit, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_dbg(dev, "start request\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pr_ctrl = readq(fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) pr_ctrl |= FME_PR_CTRL_PR_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_dbg(dev, "pushing data from bitstream to HW\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * driver can push data to PR hardware using PR_DATA register once HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * has enough pr_credit (> 1), pr_credit reduces one for every 32bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * pr data write to PR_DATA register. If pr_credit <= 1, driver needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * to wait for enough pr_credit from hardware by polling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_status = readq(fme_pr + FME_PR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) while (count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (pr_credit <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (delay++ > PR_WAIT_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_err(dev, "PR_CREDIT timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_status = readq(fme_pr + FME_PR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (count < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dev_err(dev, "Invalid PR bitstream size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pr_data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) *(((u32 *)buf) + i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writeq(pr_data, fme_pr + FME_PR_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) count -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) pr_credit--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int fme_mgr_write_complete(struct fpga_manager *mgr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct fpga_image_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct device *dev = &mgr->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct fme_mgr_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) void __iomem *fme_pr = priv->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u64 pr_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) pr_ctrl = readq(fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pr_ctrl |= FME_PR_CTRL_PR_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) writeq(pr_ctrl, fme_pr + FME_PR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dev_dbg(dev, "green bitstream push complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) dev_dbg(dev, "waiting for HW to release PR resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (readq_poll_timeout(fme_pr + FME_PR_CTRL, pr_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) !(pr_ctrl & FME_PR_CTRL_PR_START), 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PR_WAIT_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(dev, "PR Completion ACK timeout.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_dbg(dev, "PR operation complete, checking status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) priv->pr_error = fme_mgr_pr_error_handle(fme_pr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (priv->pr_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_dbg(dev, "PR error detected %llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (unsigned long long)priv->pr_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_dbg(dev, "PR done successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static enum fpga_mgr_states fme_mgr_state(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return FPGA_MGR_STATE_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static u64 fme_mgr_status(struct fpga_manager *mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct fme_mgr_priv *priv = mgr->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return pr_error_to_mgr_status(priv->pr_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const struct fpga_manager_ops fme_mgr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .write_init = fme_mgr_write_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .write = fme_mgr_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .write_complete = fme_mgr_write_complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .state = fme_mgr_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .status = fme_mgr_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static void fme_mgr_get_compat_id(void __iomem *fme_pr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct fpga_compat_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int fme_mgr_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct fpga_compat_id *compat_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct fme_mgr_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct fpga_manager *mgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (pdata->ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) priv->ioaddr = pdata->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!priv->ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) priv->ioaddr = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (IS_ERR(priv->ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return PTR_ERR(priv->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) compat_id = devm_kzalloc(dev, sizeof(*compat_id), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (!compat_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) fme_mgr_get_compat_id(priv->ioaddr, compat_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mgr = devm_fpga_mgr_create(dev, "DFL FME FPGA Manager",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) &fme_mgr_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!mgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mgr->compat_id = compat_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) platform_set_drvdata(pdev, mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return fpga_mgr_register(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int fme_mgr_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct fpga_manager *mgr = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) fpga_mgr_unregister(mgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static struct platform_driver fme_mgr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = DFL_FPGA_FME_MGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .probe = fme_mgr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .remove = fme_mgr_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_platform_driver(fme_mgr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_DESCRIPTION("FPGA Manager for DFL FPGA Management Engine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MODULE_ALIAS("platform:dfl-fme-mgr");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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