^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Management Engine (FME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/hwmon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/hwmon-sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/fpga-dfl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "dfl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "dfl-fme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static ssize_t ports_num_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) v = readq(base + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return scnprintf(buf, PAGE_SIZE, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) (unsigned int)FIELD_GET(FME_CAP_NUM_PORTS, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static DEVICE_ATTR_RO(ports_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Bitstream (static FPGA region) identifier number. It contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * detailed version and other information of this static FPGA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static ssize_t bitstream_id_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) v = readq(base + FME_HDR_BITSTREAM_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static DEVICE_ATTR_RO(bitstream_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Bitstream (static FPGA region) meta data. It contains the synthesis
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * date, seed and other information of this static FPGA region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static ssize_t bitstream_metadata_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) v = readq(base + FME_HDR_BITSTREAM_MD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return scnprintf(buf, PAGE_SIZE, "0x%llx\n", (unsigned long long)v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static DEVICE_ATTR_RO(bitstream_metadata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static ssize_t cache_size_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) v = readq(base + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) (unsigned int)FIELD_GET(FME_CAP_CACHE_SIZE, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static DEVICE_ATTR_RO(cache_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static ssize_t fabric_version_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) v = readq(base + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) (unsigned int)FIELD_GET(FME_CAP_FABRIC_VERID, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static DEVICE_ATTR_RO(fabric_version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static ssize_t socket_id_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v = readq(base + FME_HDR_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (unsigned int)FIELD_GET(FME_CAP_SOCKET_ID, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static DEVICE_ATTR_RO(socket_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct attribute *fme_hdr_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &dev_attr_ports_num.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &dev_attr_bitstream_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &dev_attr_bitstream_metadata.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &dev_attr_cache_size.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &dev_attr_fabric_version.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &dev_attr_socket_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct attribute_group fme_hdr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .attrs = fme_hdr_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (get_user(port_id, (int __user *)arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return dfl_fpga_cdev_release_port(cdev, port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static long fme_hdr_ioctl_assign_port(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dfl_fpga_cdev *cdev = pdata->dfl_cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (get_user(port_id, (int __user *)arg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return dfl_fpga_cdev_assign_port(cdev, port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static long fme_hdr_ioctl(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case DFL_FPGA_FME_PORT_RELEASE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return fme_hdr_ioctl_release_port(pdata, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) case DFL_FPGA_FME_PORT_ASSIGN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return fme_hdr_ioctl_assign_port(pdata, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct dfl_feature_id fme_hdr_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {.id = FME_FEATURE_ID_HEADER,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct dfl_feature_ops fme_hdr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .ioctl = fme_hdr_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define FME_THERM_THRESHOLD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEMP_THRESHOLD1 GENMASK_ULL(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEMP_THRESHOLD1_EN BIT_ULL(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEMP_THRESHOLD2 GENMASK_ULL(14, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEMP_THRESHOLD2_EN BIT_ULL(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TRIP_THRESHOLD GENMASK_ULL(30, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEMP_THRESHOLD1_STATUS BIT_ULL(32) /* threshold1 reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEMP_THRESHOLD2_STATUS BIT_ULL(33) /* threshold2 reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* threshold1 policy: 0 - AP2 (90% throttle) / 1 - AP1 (50% throttle) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEMP_THRESHOLD1_POLICY BIT_ULL(44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define FME_THERM_RDSENSOR_FMT1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FPGA_TEMPERATURE GENMASK_ULL(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FME_THERM_CAP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define THERM_NO_THROTTLE BIT_ULL(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MD_PRE_DEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static bool fme_thermal_throttle_support(void __iomem *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u64 v = readq(base + FME_THERM_CAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return FIELD_GET(THERM_NO_THROTTLE, v) ? false : true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static umode_t thermal_hwmon_attrs_visible(const void *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) const struct dfl_feature *feature = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* temperature is always supported, and check hardware cap for others */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (attr == hwmon_temp_input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return fme_thermal_throttle_support(feature->ioaddr) ? 0444 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int thermal_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case hwmon_temp_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) v = readq(feature->ioaddr + FME_THERM_RDSENSOR_FMT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *val = (long)(FIELD_GET(FPGA_TEMPERATURE, v) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case hwmon_temp_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) *val = (long)(FIELD_GET(TEMP_THRESHOLD1, v) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case hwmon_temp_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *val = (long)(FIELD_GET(TEMP_THRESHOLD2, v) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) case hwmon_temp_emergency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) *val = (long)(FIELD_GET(TRIP_THRESHOLD, v) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case hwmon_temp_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *val = (long)FIELD_GET(TEMP_THRESHOLD1_STATUS, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case hwmon_temp_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *val = (long)FIELD_GET(TEMP_THRESHOLD2_STATUS, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct hwmon_ops thermal_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .is_visible = thermal_hwmon_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .read = thermal_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct hwmon_channel_info *thermal_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_EMERGENCY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) HWMON_T_MAX | HWMON_T_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) HWMON_T_CRIT | HWMON_T_CRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct hwmon_chip_info thermal_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .ops = &thermal_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .info = thermal_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static ssize_t temp1_max_policy_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) v = readq(feature->ioaddr + FME_THERM_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (unsigned int)FIELD_GET(TEMP_THRESHOLD1_POLICY, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static DEVICE_ATTR_RO(temp1_max_policy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct attribute *thermal_extra_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) &dev_attr_temp1_max_policy.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static umode_t thermal_extra_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct attribute *attr, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return fme_thermal_throttle_support(feature->ioaddr) ? attr->mode : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct attribute_group thermal_extra_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .attrs = thermal_extra_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .is_visible = thermal_extra_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __ATTRIBUTE_GROUPS(thermal_extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int fme_thermal_mgmt_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * create hwmon to allow userspace monitoring temperature and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * threshold information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * temp1_input -> FPGA device temperature
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * temp1_max -> hardware threshold 1 -> 50% or 90% throttling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * temp1_crit -> hardware threshold 2 -> 100% throttling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * temp1_emergency -> hardware trip_threshold to shutdown FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * temp1_max_alarm -> hardware threshold 1 alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * temp1_crit_alarm -> hardware threshold 2 alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * create device specific sysfs interfaces, e.g. read temp1_max_policy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * to understand the actual hardware throttling action (50% vs 90%).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * If hardware doesn't support automatic throttling per thresholds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * then all above sysfs interfaces are not visible except temp1_input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * for temperature.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "dfl_fme_thermal", feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) &thermal_hwmon_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) thermal_extra_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (IS_ERR(hwmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(&pdev->dev, "Fail to register thermal hwmon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return PTR_ERR(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const struct dfl_feature_id fme_thermal_mgmt_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {.id = FME_FEATURE_ID_THERMAL_MGMT,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct dfl_feature_ops fme_thermal_mgmt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .init = fme_thermal_mgmt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define FME_PWR_STATUS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define FME_LATENCY_TOLERANCE BIT_ULL(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PWR_CONSUMED GENMASK_ULL(17, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define FME_PWR_THRESHOLD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PWR_THRESHOLD1 GENMASK_ULL(6, 0) /* in Watts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PWR_THRESHOLD2 GENMASK_ULL(14, 8) /* in Watts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define PWR_THRESHOLD_MAX 0x7f /* in Watts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define PWR_THRESHOLD1_STATUS BIT_ULL(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define PWR_THRESHOLD2_STATUS BIT_ULL(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define FME_PWR_XEON_LIMIT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define XEON_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define XEON_PWR_EN BIT_ULL(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define FME_PWR_FPGA_LIMIT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define FPGA_PWR_LIMIT GENMASK_ULL(14, 0) /* in 0.1 Watts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define FPGA_PWR_EN BIT_ULL(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int power_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 attr, int channel, long *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case hwmon_power_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) v = readq(feature->ioaddr + FME_PWR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *val = (long)(FIELD_GET(PWR_CONSUMED, v) * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case hwmon_power_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *val = (long)(FIELD_GET(PWR_THRESHOLD1, v) * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) case hwmon_power_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) *val = (long)(FIELD_GET(PWR_THRESHOLD2, v) * 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case hwmon_power_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *val = (long)FIELD_GET(PWR_THRESHOLD1_STATUS, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case hwmon_power_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) *val = (long)FIELD_GET(PWR_THRESHOLD2_STATUS, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int power_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 attr, int channel, long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) val = clamp_val(val / 1000000, 0, PWR_THRESHOLD_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case hwmon_power_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) v &= ~PWR_THRESHOLD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) v |= FIELD_PREP(PWR_THRESHOLD1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case hwmon_power_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) v = readq(feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) v &= ~PWR_THRESHOLD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) v |= FIELD_PREP(PWR_THRESHOLD2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) writeq(v, feature->ioaddr + FME_PWR_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static umode_t power_hwmon_attrs_visible(const void *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) enum hwmon_sensor_types type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 attr, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) switch (attr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case hwmon_power_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case hwmon_power_max_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case hwmon_power_crit_alarm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0444;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) case hwmon_power_max:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case hwmon_power_crit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return 0644;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct hwmon_ops power_hwmon_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .is_visible = power_hwmon_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .read = power_hwmon_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .write = power_hwmon_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct hwmon_channel_info *power_hwmon_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) HWMON_CHANNEL_INFO(power, HWMON_P_INPUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) HWMON_P_MAX | HWMON_P_MAX_ALARM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) HWMON_P_CRIT | HWMON_P_CRIT_ALARM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct hwmon_chip_info power_hwmon_chip_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .ops = &power_hwmon_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .info = power_hwmon_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static ssize_t power1_xeon_limit_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u16 xeon_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) v = readq(feature->ioaddr + FME_PWR_XEON_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (FIELD_GET(XEON_PWR_EN, v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) xeon_limit = FIELD_GET(XEON_PWR_LIMIT, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return sprintf(buf, "%u\n", xeon_limit * 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static ssize_t power1_fpga_limit_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 fpga_limit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) v = readq(feature->ioaddr + FME_PWR_FPGA_LIMIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (FIELD_GET(FPGA_PWR_EN, v))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fpga_limit = FIELD_GET(FPGA_PWR_LIMIT, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return sprintf(buf, "%u\n", fpga_limit * 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static ssize_t power1_ltr_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct dfl_feature *feature = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) v = readq(feature->ioaddr + FME_PWR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return sprintf(buf, "%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) (unsigned int)FIELD_GET(FME_LATENCY_TOLERANCE, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static DEVICE_ATTR_RO(power1_xeon_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static DEVICE_ATTR_RO(power1_fpga_limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static DEVICE_ATTR_RO(power1_ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static struct attribute *power_extra_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &dev_attr_power1_xeon_limit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &dev_attr_power1_fpga_limit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &dev_attr_power1_ltr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ATTRIBUTE_GROUPS(power_extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int fme_power_mgmt_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct device *hwmon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) hwmon = devm_hwmon_device_register_with_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "dfl_fme_power", feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) &power_hwmon_chip_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) power_extra_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (IS_ERR(hwmon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(&pdev->dev, "Fail to register power hwmon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return PTR_ERR(hwmon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct dfl_feature_id fme_power_mgmt_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {.id = FME_FEATURE_ID_POWER_MGMT,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const struct dfl_feature_ops fme_power_mgmt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .init = fme_power_mgmt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct dfl_feature_driver fme_feature_drvs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .id_table = fme_hdr_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .ops = &fme_hdr_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .id_table = fme_pr_mgmt_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .ops = &fme_pr_mgmt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .id_table = fme_global_err_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .ops = &fme_global_err_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .id_table = fme_thermal_mgmt_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &fme_thermal_mgmt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .id_table = fme_power_mgmt_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .ops = &fme_power_mgmt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .id_table = fme_perf_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .ops = &fme_perf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .ops = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static long fme_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* No extension support for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int fme_open(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct dfl_feature_platform_data *pdata = dev_get_platdata(&fdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (WARN_ON(!pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_dbg(&fdev->dev, "Device File Opened %d Times\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dfl_feature_dev_use_count(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) filp->private_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int fme_release(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct dfl_feature_platform_data *pdata = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct platform_device *pdev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct dfl_feature *feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) dev_dbg(&pdev->dev, "Device File Release\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dfl_feature_dev_use_end(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (!dfl_feature_dev_use_count(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dfl_fpga_dev_for_each_feature(pdata, feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dfl_fpga_set_irq_triggers(feature, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) feature->nr_irqs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static long fme_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct dfl_feature_platform_data *pdata = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct platform_device *pdev = pdata->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct dfl_feature *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case DFL_FPGA_GET_API_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return DFL_FPGA_API_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case DFL_FPGA_CHECK_EXTENSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return fme_ioctl_check_extension(pdata, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Let sub-feature's ioctl function to handle the cmd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Sub-feature's ioctl returns -ENODEV when cmd is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * handled in this sub feature, and returns 0 or other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * error code if cmd is handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dfl_fpga_dev_for_each_feature(pdata, f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (f->ops && f->ops->ioctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = f->ops->ioctl(pdev, f, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int fme_dev_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct dfl_fme *fme;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) fme = devm_kzalloc(&pdev->dev, sizeof(*fme), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!fme)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) fme->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dfl_fpga_pdata_set_private(pdata, fme);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void fme_dev_destroy(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dfl_fpga_pdata_set_private(pdata, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct file_operations fme_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .open = fme_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .release = fme_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .unlocked_ioctl = fme_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int fme_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = fme_dev_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = dfl_fpga_dev_feature_init(pdev, fme_feature_drvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) goto dev_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = dfl_fpga_dev_ops_register(pdev, &fme_fops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto feature_uinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) feature_uinit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dfl_fpga_dev_feature_uinit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dev_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) fme_dev_destroy(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int fme_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dfl_fpga_dev_ops_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dfl_fpga_dev_feature_uinit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) fme_dev_destroy(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct attribute_group *fme_dev_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) &fme_hdr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) &fme_global_err_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static struct platform_driver fme_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = DFL_FPGA_FEATURE_DEV_FME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .dev_groups = fme_dev_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .probe = fme_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .remove = fme_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) module_platform_driver(fme_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MODULE_DESCRIPTION("FPGA Management Engine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) MODULE_ALIAS("platform:dfl-fme");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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