^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Management Engine Error Management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2019 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kang Luwei <luwei.kang@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Mitchel, Henry <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fpga-dfl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "dfl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dfl-fme.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FME_ERROR_MASK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FME_ERROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MBP_ERROR BIT_ULL(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCIE0_ERROR_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCIE0_ERROR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PCIE1_ERROR_MASK 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCIE1_ERROR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FME_FIRST_ERROR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FME_NEXT_ERROR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RAS_NONFAT_ERROR_MASK 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RAS_NONFAT_ERROR 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RAS_CATFAT_ERROR_MASK 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RAS_CATFAT_ERROR 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RAS_ERROR_INJECT 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define INJECT_ERROR_MASK GENMASK_ULL(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ERROR_MASK GENMASK_ULL(63, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static ssize_t pcie0_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) value = readq(base + PCIE0_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return sprintf(buf, "0x%llx\n", (unsigned long long)value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static ssize_t pcie0_errors_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 v, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (kstrtou64(buf, 0, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) v = readq(base + PCIE0_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (val == v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writeq(v, base + PCIE0_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writeq(0ULL, base + PCIE0_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ret ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static DEVICE_ATTR_RW(pcie0_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static ssize_t pcie1_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) value = readq(base + PCIE1_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return sprintf(buf, "0x%llx\n", (unsigned long long)value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static ssize_t pcie1_errors_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u64 v, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (kstrtou64(buf, 0, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) v = readq(base + PCIE1_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (val == v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writeq(v, base + PCIE1_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) writeq(0ULL, base + PCIE1_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static DEVICE_ATTR_RW(pcie1_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static ssize_t nonfatal_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return sprintf(buf, "0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) (unsigned long long)readq(base + RAS_NONFAT_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static DEVICE_ATTR_RO(nonfatal_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static ssize_t catfatal_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return sprintf(buf, "0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (unsigned long long)readq(base + RAS_CATFAT_ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static DEVICE_ATTR_RO(catfatal_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static ssize_t inject_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) v = readq(base + RAS_ERROR_INJECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return sprintf(buf, "0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) (unsigned long long)FIELD_GET(INJECT_ERROR_MASK, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static ssize_t inject_errors_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 inject_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (kstrtou8(buf, 0, &inject_error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (inject_error & ~INJECT_ERROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) v = readq(base + RAS_ERROR_INJECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) v &= ~INJECT_ERROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) v |= FIELD_PREP(INJECT_ERROR_MASK, inject_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) writeq(v, base + RAS_ERROR_INJECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static DEVICE_ATTR_RW(inject_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static ssize_t fme_errors_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) value = readq(base + FME_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return sprintf(buf, "0x%llx\n", (unsigned long long)value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static ssize_t fme_errors_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u64 v, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (kstrtou64(buf, 0, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) v = readq(base + FME_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (val == v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) writeq(v, base + FME_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Workaround: disable MBP_ERROR if feature revision is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) base + FME_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ret ? ret : count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static DEVICE_ATTR_RW(fme_errors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static ssize_t first_error_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) value = readq(base + FME_FIRST_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return sprintf(buf, "0x%llx\n", (unsigned long long)value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static DEVICE_ATTR_RO(first_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static ssize_t next_error_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) value = readq(base + FME_NEXT_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return sprintf(buf, "0x%llx\n", (unsigned long long)value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static DEVICE_ATTR_RO(next_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct attribute *fme_global_err_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) &dev_attr_pcie0_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &dev_attr_pcie1_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &dev_attr_nonfatal_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &dev_attr_catfatal_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) &dev_attr_inject_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &dev_attr_fme_errors.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) &dev_attr_first_error.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) &dev_attr_next_error.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static umode_t fme_global_err_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct attribute *attr, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * sysfs entries are visible only if related private feature is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * enumerated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!dfl_get_feature_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) const struct attribute_group fme_global_err_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .name = "errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .attrs = fme_global_err_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .is_visible = fme_global_err_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static void fme_err_mask(struct device *dev, bool mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Workaround: keep MBP_ERROR always masked if revision is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (dfl_feature_revision(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int fme_global_err_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fme_err_mask(&pdev->dev, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void fme_global_err_uinit(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fme_err_mask(&pdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) fme_global_error_ioctl(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) case DFL_FPGA_FME_ERR_GET_IRQ_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return dfl_feature_ioctl_get_num_irqs(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case DFL_FPGA_FME_ERR_SET_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return dfl_feature_ioctl_set_irq(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) const struct dfl_feature_id fme_global_err_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {.id = FME_FEATURE_ID_GLOBAL_ERR,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const struct dfl_feature_ops fme_global_err_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .init = fme_global_err_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .uinit = fme_global_err_uinit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .ioctl = fme_global_error_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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