Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * FPGA Bridge Driver for FPGA Management Engine (FME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *   Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *   Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *   Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *   Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *   Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *   Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/fpga/fpga-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "dfl.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "dfl-fme-pr.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) struct fme_br_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct dfl_fme_br_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct dfl_fpga_port_ops *port_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct platform_device *port_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static int fme_bridge_enable_set(struct fpga_bridge *bridge, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct fme_br_priv *priv = bridge->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct platform_device *port_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	struct dfl_fpga_port_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	if (!priv->port_pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		port_pdev = dfl_fpga_cdev_find_port(priv->pdata->cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 						    &priv->pdata->port_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 						    dfl_fpga_check_port_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		if (!port_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		priv->port_pdev = port_pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	if (priv->port_pdev && !priv->port_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		ops = dfl_fpga_port_ops_get(priv->port_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		if (!ops || !ops->enable_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 			return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		priv->port_ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return priv->port_ops->enable_set(priv->port_pdev, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static const struct fpga_bridge_ops fme_bridge_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.enable_set = fme_bridge_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static int fme_br_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct fme_br_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct fpga_bridge *br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	priv->pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	br = devm_fpga_bridge_create(dev, "DFL FPGA FME Bridge",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				     &fme_bridge_ops, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	if (!br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	platform_set_drvdata(pdev, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	return fpga_bridge_register(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static int fme_br_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	struct fpga_bridge *br = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct fme_br_priv *priv = br->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	fpga_bridge_unregister(br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	if (priv->port_pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		put_device(&priv->port_pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (priv->port_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		dfl_fpga_port_ops_put(priv->port_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static struct platform_driver fme_br_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.driver	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.name    = DFL_FPGA_FME_BRIDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.probe   = fme_br_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.remove  = fme_br_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) module_platform_driver(fme_br_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MODULE_DESCRIPTION("FPGA Bridge for DFL FPGA Management Engine");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_ALIAS("platform:dfl-fme-bridge");