^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for FPGA Accelerated Function Unit (AFU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017-2018 Intel Corporation, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Wu Hao <hao.wu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Xiao Guangrong <guangrong.xiao@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Joseph Grecco <joe.grecco@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Enno Luebbers <enno.luebbers@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Tim Whisonant <tim.whisonant@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Ananda Ravuri <ananda.ravuri@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Henry Mitchel <henry.mitchel@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fpga-dfl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "dfl-afu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * __afu_port_enable - enable a port by clear reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @pdev: port platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Enable Port by clear the port soft reset bit, which is set by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The AFU is unable to respond to any MMIO access while in reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * __afu_port_enable function should only be used after __afu_port_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * The caller needs to hold lock for protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void __afu_port_enable(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) WARN_ON(!pdata->disable_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) if (--pdata->disable_count != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Clear port soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) v = readq(base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) v &= ~PORT_CTRL_SFTRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writeq(v, base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RST_POLL_INVL 10 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RST_POLL_TIMEOUT 1000 /* us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * __afu_port_disable - disable a port by hold reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pdev: port platform device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Disable Port by setting the port soft reset bit, it puts the port into reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * The caller needs to hold lock for protection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int __afu_port_disable(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (pdata->disable_count++ != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Set port soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) v = readq(base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) v |= PORT_CTRL_SFTRST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writeq(v, base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * HW sets ack bit to 1 when all outstanding requests have been drained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * on this port and minimum soft reset pulse width has elapsed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Driver polls port_soft_reset_ack to determine if reset done by HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) v & PORT_CTRL_SFTRST_ACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) RST_POLL_INVL, RST_POLL_TIMEOUT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dev_err(&pdev->dev, "timeout, fail to reset device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * This function resets the FPGA Port and its accelerator (AFU) by function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * __port_disable and __port_enable (set port soft reset bit and then clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * it). Userspace can do Port reset at any time, e.g. during DMA or Partial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Reconfiguration. But it should never cause any system level issue, only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * functional failure (e.g. DMA or PR operation failure) and be recoverable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * from the failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Note: the accelerator (AFU) is not accessible when its port is in reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * (disabled). Any attempts on MMIO access to AFU while in reset, will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * result errors reported via port error reporting sub feature (if present).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int __port_reset(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = __afu_port_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __afu_port_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int port_reset(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ret = __port_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int port_get_id(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return FIELD_GET(PORT_CAP_PORT_NUM, readq(base + PORT_HDR_CAP));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) id_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int id = port_get_id(to_platform_device(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return scnprintf(buf, PAGE_SIZE, "%d\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static DEVICE_ATTR_RO(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ltr_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) v = readq(base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_CTRL_LATENCY, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ltr_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool ltr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (kstrtobool(buf, <r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) v = readq(base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) v &= ~PORT_CTRL_LATENCY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) v |= FIELD_PREP(PORT_CTRL_LATENCY, ltr ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writeq(v, base + PORT_HDR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static DEVICE_ATTR_RW(ltr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ap1_event_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) v = readq(base + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP1_EVT, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ap1_event_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) bool clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (kstrtobool(buf, &clear) || !clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writeq(PORT_STS_AP1_EVT, base + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static DEVICE_ATTR_RW(ap1_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ap2_event_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) v = readq(base + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return sprintf(buf, "%x\n", (u8)FIELD_GET(PORT_STS_AP2_EVT, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ap2_event_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (kstrtobool(buf, &clear) || !clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writeq(PORT_STS_AP2_EVT, base + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static DEVICE_ATTR_RW(ap2_event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) power_state_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u64 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) v = readq(base + PORT_HDR_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return sprintf(buf, "0x%x\n", (u8)FIELD_GET(PORT_STS_PWR_STATE, v));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static DEVICE_ATTR_RO(power_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) userclk_freqcmd_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u64 userclk_freq_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (kstrtou64(buf, 0, &userclk_freq_cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) writeq(userclk_freq_cmd, base + PORT_HDR_USRCLK_CMD0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static DEVICE_ATTR_WO(userclk_freqcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) userclk_freqcntrcmd_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u64 userclk_freqcntr_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (kstrtou64(buf, 0, &userclk_freqcntr_cmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writeq(userclk_freqcntr_cmd, base + PORT_HDR_USRCLK_CMD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static DEVICE_ATTR_WO(userclk_freqcntrcmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) userclk_freqsts_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u64 userclk_freqsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) userclk_freqsts = readq(base + PORT_HDR_USRCLK_STS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return sprintf(buf, "0x%llx\n", (unsigned long long)userclk_freqsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static DEVICE_ATTR_RO(userclk_freqsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) userclk_freqcntrsts_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u64 userclk_freqcntrsts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) userclk_freqcntrsts = readq(base + PORT_HDR_USRCLK_STS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return sprintf(buf, "0x%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (unsigned long long)userclk_freqcntrsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static DEVICE_ATTR_RO(userclk_freqcntrsts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct attribute *port_hdr_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) &dev_attr_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) &dev_attr_ltr.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) &dev_attr_ap1_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) &dev_attr_ap2_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) &dev_attr_power_state.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) &dev_attr_userclk_freqcmd.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) &dev_attr_userclk_freqcntrcmd.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) &dev_attr_userclk_freqsts.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) &dev_attr_userclk_freqcntrsts.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static umode_t port_hdr_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct attribute *attr, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) umode_t mode = attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_HEADER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (dfl_feature_revision(base) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * userclk sysfs interfaces are only visible in case port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * revision is 0, as hardware with revision >0 doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * support this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (attr == &dev_attr_userclk_freqcmd.attr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) attr == &dev_attr_userclk_freqcntrcmd.attr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) attr == &dev_attr_userclk_freqsts.attr ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) attr == &dev_attr_userclk_freqcntrsts.attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct attribute_group port_hdr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .attrs = port_hdr_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .is_visible = port_hdr_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static int port_hdr_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) port_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) port_hdr_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case DFL_FPGA_PORT_RESET:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ret = port_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static const struct dfl_feature_id port_hdr_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {.id = PORT_FEATURE_ID_HEADER,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct dfl_feature_ops port_hdr_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .init = port_hdr_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ioctl = port_hdr_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static ssize_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) afu_id_show(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u64 guidl, guidh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) base = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_AFU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (pdata->disable_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) guidl = readq(base + GUID_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) guidh = readq(base + GUID_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static DEVICE_ATTR_RO(afu_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct attribute *port_afu_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) &dev_attr_afu_id.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static umode_t port_afu_attrs_visible(struct kobject *kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct attribute *attr, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct device *dev = kobj_to_dev(kobj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * sysfs entries are visible only if related private feature is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * enumerated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (!dfl_get_feature_by_id(dev, PORT_FEATURE_ID_AFU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return attr->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const struct attribute_group port_afu_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .attrs = port_afu_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .is_visible = port_afu_attrs_visible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int port_afu_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct resource *res = &pdev->resource[feature->resource_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return afu_mmio_region_add(dev_get_platdata(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DFL_PORT_REGION_INDEX_AFU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) resource_size(res), res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DFL_PORT_REGION_MMAP | DFL_PORT_REGION_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DFL_PORT_REGION_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct dfl_feature_id port_afu_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {.id = PORT_FEATURE_ID_AFU,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct dfl_feature_ops port_afu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .init = port_afu_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int port_stp_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct dfl_feature *feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct resource *res = &pdev->resource[feature->resource_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return afu_mmio_region_add(dev_get_platdata(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DFL_PORT_REGION_INDEX_STP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) resource_size(res), res->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DFL_PORT_REGION_MMAP | DFL_PORT_REGION_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DFL_PORT_REGION_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const struct dfl_feature_id port_stp_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {.id = PORT_FEATURE_ID_STP,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct dfl_feature_ops port_stp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .init = port_stp_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) port_uint_ioctl(struct platform_device *pdev, struct dfl_feature *feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case DFL_FPGA_PORT_UINT_GET_IRQ_NUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return dfl_feature_ioctl_get_num_irqs(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case DFL_FPGA_PORT_UINT_SET_IRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return dfl_feature_ioctl_set_irq(pdev, feature, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dev_dbg(&pdev->dev, "%x cmd not handled", cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const struct dfl_feature_id port_uint_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {.id = PORT_FEATURE_ID_UINT,},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct dfl_feature_ops port_uint_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .ioctl = port_uint_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct dfl_feature_driver port_feature_drvs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .id_table = port_hdr_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ops = &port_hdr_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .id_table = port_afu_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .ops = &port_afu_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .id_table = port_err_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .ops = &port_err_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .id_table = port_stp_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .ops = &port_stp_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .id_table = port_uint_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &port_uint_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .ops = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int afu_open(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct platform_device *fdev = dfl_fpga_inode_to_feature_dev(inode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct dfl_feature_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) pdata = dev_get_platdata(&fdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (WARN_ON(!pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = dfl_feature_dev_use_begin(pdata, filp->f_flags & O_EXCL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) dev_dbg(&fdev->dev, "Device File Opened %d Times\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dfl_feature_dev_use_count(pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) filp->private_data = fdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int afu_release(struct inode *inode, struct file *filp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct platform_device *pdev = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct dfl_feature_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct dfl_feature *feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) dev_dbg(&pdev->dev, "Device File Release\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dfl_feature_dev_use_end(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!dfl_feature_dev_use_count(pdata)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dfl_fpga_dev_for_each_feature(pdata, feature)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dfl_fpga_set_irq_triggers(feature, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) feature->nr_irqs, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) __port_reset(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) afu_dma_region_destroy(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static long afu_ioctl_check_extension(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* No extension support for now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) afu_ioctl_get_info(struct dfl_feature_platform_data *pdata, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct dfl_fpga_port_info info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct dfl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) minsz = offsetofend(struct dfl_fpga_port_info, num_umsgs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (copy_from_user(&info, arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (info.argsz < minsz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) afu = dfl_fpga_pdata_get_private(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) info.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) info.num_regions = afu->num_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) info.num_umsgs = afu->num_umsgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (copy_to_user(arg, &info, sizeof(info)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static long afu_ioctl_get_region_info(struct dfl_feature_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct dfl_fpga_port_region_info rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct dfl_afu_mmio_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) minsz = offsetofend(struct dfl_fpga_port_region_info, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (copy_from_user(&rinfo, arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (rinfo.argsz < minsz || rinfo.padding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = afu_mmio_region_get_by_index(pdata, rinfo.index, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) rinfo.flags = region.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) rinfo.size = region.size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rinfo.offset = region.offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (copy_to_user(arg, &rinfo, sizeof(rinfo)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) afu_ioctl_dma_map(struct dfl_feature_platform_data *pdata, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct dfl_fpga_port_dma_map map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) minsz = offsetofend(struct dfl_fpga_port_dma_map, iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (copy_from_user(&map, arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (map.argsz < minsz || map.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = afu_dma_map_region(pdata, map.user_addr, map.length, &map.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (copy_to_user(arg, &map, sizeof(map))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) afu_dma_unmap_region(pdata, map.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_dbg(&pdata->dev->dev, "dma map: ua=%llx, len=%llx, iova=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) (unsigned long long)map.user_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) (unsigned long long)map.length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) (unsigned long long)map.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) afu_ioctl_dma_unmap(struct dfl_feature_platform_data *pdata, void __user *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct dfl_fpga_port_dma_unmap unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) unsigned long minsz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) minsz = offsetofend(struct dfl_fpga_port_dma_unmap, iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (copy_from_user(&unmap, arg, minsz))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (unmap.argsz < minsz || unmap.flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return afu_dma_unmap_region(pdata, unmap.iova);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static long afu_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct platform_device *pdev = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct dfl_feature_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct dfl_feature *f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_dbg(&pdev->dev, "%s cmd 0x%x\n", __func__, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case DFL_FPGA_GET_API_VERSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return DFL_FPGA_API_VERSION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case DFL_FPGA_CHECK_EXTENSION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return afu_ioctl_check_extension(pdata, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case DFL_FPGA_PORT_GET_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return afu_ioctl_get_info(pdata, (void __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case DFL_FPGA_PORT_GET_REGION_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return afu_ioctl_get_region_info(pdata, (void __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case DFL_FPGA_PORT_DMA_MAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return afu_ioctl_dma_map(pdata, (void __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case DFL_FPGA_PORT_DMA_UNMAP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return afu_ioctl_dma_unmap(pdata, (void __user *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * Let sub-feature's ioctl function to handle the cmd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Sub-feature's ioctl returns -ENODEV when cmd is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * handled in this sub feature, and returns 0 and other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * error code if cmd is handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dfl_fpga_dev_for_each_feature(pdata, f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (f->ops && f->ops->ioctl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = f->ops->ioctl(pdev, f, cmd, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct vm_operations_struct afu_vma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #ifdef CONFIG_HAVE_IOREMAP_PROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .access = generic_access_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int afu_mmap(struct file *filp, struct vm_area_struct *vma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct platform_device *pdev = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct dfl_feature_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u64 size = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct dfl_afu_mmio_region region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u64 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!(vma->vm_flags & VM_SHARED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) offset = vma->vm_pgoff << PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = afu_mmio_region_get_by_offset(pdata, offset, size, ®ion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!(region.flags & DFL_PORT_REGION_MMAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if ((vma->vm_flags & VM_READ) && !(region.flags & DFL_PORT_REGION_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if ((vma->vm_flags & VM_WRITE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) !(region.flags & DFL_PORT_REGION_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Support debug access to the mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) vma->vm_ops = &afu_vma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) (region.phys + (offset - region.offset)) >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) size, vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const struct file_operations afu_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .open = afu_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .release = afu_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .unlocked_ioctl = afu_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .mmap = afu_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int afu_dev_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) struct dfl_afu *afu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) afu = devm_kzalloc(&pdev->dev, sizeof(*afu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (!afu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) afu->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dfl_fpga_pdata_set_private(pdata, afu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) afu_mmio_region_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) afu_dma_region_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int afu_dev_destroy(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) afu_mmio_region_destroy(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) afu_dma_region_destroy(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dfl_fpga_pdata_set_private(pdata, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int port_enable_set(struct platform_device *pdev, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) mutex_lock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __afu_port_enable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = __afu_port_disable(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) mutex_unlock(&pdata->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static struct dfl_fpga_port_ops afu_port_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .name = DFL_FPGA_FEATURE_DEV_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .get_id = port_get_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .enable_set = port_enable_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static int afu_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dev_dbg(&pdev->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = afu_dev_init(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = dfl_fpga_dev_feature_init(pdev, port_feature_drvs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) goto dev_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = dfl_fpga_dev_ops_register(pdev, &afu_fops, THIS_MODULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dfl_fpga_dev_feature_uinit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) goto dev_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) afu_dev_destroy(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static int afu_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) dev_dbg(&pdev->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) dfl_fpga_dev_ops_unregister(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dfl_fpga_dev_feature_uinit(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) afu_dev_destroy(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const struct attribute_group *afu_dev_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) &port_hdr_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) &port_afu_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) &port_err_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static struct platform_driver afu_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = DFL_FPGA_FEATURE_DEV_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .dev_groups = afu_dev_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .probe = afu_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .remove = afu_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int __init afu_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dfl_fpga_port_ops_add(&afu_port_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = platform_driver_register(&afu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dfl_fpga_port_ops_del(&afu_port_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static void __exit afu_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) platform_driver_unregister(&afu_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dfl_fpga_port_ops_del(&afu_port_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) module_init(afu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) module_exit(afu_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MODULE_DESCRIPTION("FPGA Accelerated Function Unit driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) MODULE_AUTHOR("Intel Corporation");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) MODULE_ALIAS("platform:dfl-port");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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